Texas Instruments DRA72 Series, Руководство пользователя, Страница: 24 / 39

NOR Memory
QSPI Memory
QSPI1
QSPI1_SCLK, _D[3:0], _CS[0],
_RTCLK
Mux
A
A1 B1
B2
R-Mux
GPMC_A[18:13], _CS[2]
SoC
GPMC
GPMC_A[18:13], _CS[2]
Signal Multiplex Logic
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24 SPRUIB9 – December 2016
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DRA72x EVM CPU Board User's Guide
4.1 GPMC and QSPI Selection (Mux A)
Figure 7 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): A[18:13]
• Quad Serial Bus (QSPI): SCLK, D[3:0], CS[0], RTCLK
Figure 7. SoC Pinmux for GPMC and QSPI
Mux A: Selects between NOR and QSPI memory support.
NOTE: The mux is implemented using resistors. This was due to the signal rate and routing
restrictions of the QSPI device. To enable the GPMC signals to NOR (shown in RED in
Figure 8 ), the board must be modified to move resistors.
Figure 8. Mux Diagram for GPMC and QSPI
4.2 GPMC/VIN1/VOUT3 Selection (Mux B)
Figure 9 is part of the SoC pinmux table for GPMC. The SoC device supports additional functions not
shown in the table. The functions shown are intended to reflect those supported on the EVM. These
include:
• Memory Bus (GPMC): AD[15:0], A[12:0]
• Video Input Port (VIN1A): CLK, HSYNC, VSYNC, DE, D[23:0]
• Video Output Port (VOUT3): CLK, HSYNC, VSYNC, DE, D[23:0]
• Boot Mode Selection (SYSBOOT): SYSBOOT[15:0]