Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
10
4 Clock Distribution - MAC Interface Clocking
After power-up the PHYs are configured to implement parallel RMII MAC interfaces.
PHY1 is configured in RMII master mode and is responsible to generate all necessary clocks
for the 2nd PHY (PHY2) as well as the MAC interfaces. PHY1 needs a 25MHz clock reference
on its X1 clock input, which must be provided by the application through the HSMC connector.
The MAC interface is synchronous to the 50MHz reference clock provided by PHY1. PHY1
provides the RMII interface clock on its
rx_clk
and
tx_clk
outputs.
The PHYs are configured (see Strap Options, see section 5.2) to provide the internal
synchronized IEEE 1588 clock on its
clk_out
pin, which is available to the HSMC for use by
1588 related functions of the application.
3
National PHY 1
DP83640
(RMII Master)
National PHY 2
DP83640
(RMII Slave)
RMII
50MHz
X1
X1
50MHz
rx_clk
tx_clk
50MHz Reference to MAC
clk_out
PTP Clock
Clock Distribution
HSMC Connector
RMII
gpio9
gpio9
Reference to FPGA for PTP time
related logic (25MHz)
25MHz ref
Reference from FPGA
(25MHz)
clk_out_1
ref_clk_x1
clk_out
PTP Clock
clk_out_0
Figure 6: Clock Distribution
Note:
gpio9 is connected in-between both PHY devices exclusively to allow synchronization of the
internal 1588 timers of both devices during operation.