Registers
884
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.13.11 VCOMP_reg10 Register (offset = 28h) [reset = 0h]
VCOMP_reg10 is shown in
and described in
Figure 1-560. VCOMP_reg10 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG_DSPLY_TIMEOUT_COUNT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-477. VCOMP_reg10 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CFG_DSPLY_TIMEOUT_
COUNT
R/W
0h
Timeout counter in DSS system clock cycles. An internal counter is
reset to this value following a vpi_fp pulse to the VCOMP module.
The VCOMP will start sending data to the downsteam module after
the counter counts down to 0. The NF will be sent downstream
based on the Main or Aux NF arrivals and the setting for
cfg_nf_handling. The NF output will not be delayed. Likewise.. the
Main and Aux request of data from the upstream modules are not
delayed. Only the downstream output of pixel data is delayed.
Generally.. this register should be set to 0x0.