Registers
774
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.20 HD_VENC_D_cfg19 Register (offset = 4Ch) [reset = 0h]
HD_VENC_D_cfg19 is shown in
and described in
DVO Control Register
Figure 1-456. HD_VENC_D_cfg19 Register
31
30
29
28
27
26
25
24
DVO_VS_WD2
R/W-0h
23
22
21
20
19
18
17
16
DVO_FID_ST1
R/W-0h
15
14
13
12
11
10
9
8
DVO_FID_ST1
DVO_VS_ST2
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
DVO_VS_ST2
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-369. HD_VENC_D_cfg19 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
DVO_VS_WD2
R/W
0h
Defines the width of the DVO_VS pulse of the second field (in
number of lines)
23-12
DVO_FID_ST1
R/W
0h
This parameter defines the top field line number at which the
DVO_FID will switch (only applicable in the interlaced mode).
11-0
DVO_VS_ST2
R/W
0h
Defines the starting location of the DVO_VS of the second field. This
parameter is only used in interlace mode.