Registers
762
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.8
HD_VENC_D_cfg7 Register (offset = 1Ch) [reset = 0h]
HD_VENC_D_cfg7 is shown in
and described in
Reserved Register
Figure 1-444. HD_VENC_D_cfg7 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-357. HD_VENC_D_cfg7 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
Reserved
R
0h
Reserved