Registers
761
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.7
HD_VENC_D_cfg6 Register (offset = 18h) [reset = 0h]
HD_VENC_D_cfg6 is shown in
and described in
Color Space Converter Coefficient Register
Figure 1-443. HD_VENC_D_cfg6 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
D2
R/W-0h
15
14
13
12
11
10
9
8
D2
D1
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
D1
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-356. HD_VENC_D_cfg6 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
Reserved
R
0h
Reserved
23-12
D2
R/W
0h
Coefficients of color space converter. This coefficient is an integer
number in the range of -2048 to 2047. It is in 12-bit wide 2's
compliment format. The MSB is sign bit. (Same format conversion as
D0 in HD_VENC_D_cfg5)
11-0
D1
R/W
0h
Coefficients of color space converter. This coefficient is an integer
number in the range of -2048 to 2047. It is in 12-bit wide 2's
compliment format. The MSB is sign bit. (Same format conversion as
D0 in HD_VENC_D_cfg5)