Texas Instruments DM38x DaVinci, Руководство пользователя

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VPDMA
ALIGN
SC_M
420 Current
SC out
422
YUV
To
VIP1
Subsystem
To
YUV422
Compositor
16
20
20
[9:
2]
20
{[8], 2’d0}
16
CHR_US
UV Y
8 8x4
{[
8
],
2
’d
0
}
VC1
[9
:2
]
10x4
10
8
8 8x4
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Description of the Subsystem
37 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
Figure 1-3 provides a more detailed view of the Auxiliary Input Path (AUX), showing the interconnection
between various modules and bit widths.
Figure 1-3. Auxiliary Input Path Detailed Block Diagram
The previous diagrams show the details of the interconnect and selections possible within the Video Input
Ports. In
Figure 1-4 , the signals shown on the Video Input Port Parser (VIP_PARSER) module are the
outputs generated by this module. External video input drives the input side of this module. A_Y can be in
either YUV422 format (A_Y[7:0] in the diagram) or RGB/YUV444 format (A_Y[23:0] in the diagram)
depending on the external video input source and configuration options within the VIP_PARSER. If the
VIP_PARSER is configured to capture 24bit RGB/444 data, A_Y[23:0] is used and the data path inside the
Video Input Port must be configured correctly for it. Multiplexor selections and controls are shown above,
and described in CLKC VIN0/2 Data Path Register. The output of the Video Input Port drives the VPDMA
module, which sends the resulting video to SDRAM.