Registers
342
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.3.5
COMP_sd_settings Register (offset = 10h) [reset = E400h]
COMP_sd_settings is shown in
and described in
.
Figure 1-234. COMP_sd_settings Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
FB_SEL
R-0h
R/W-0h
15
14
13
12
11
10
9
8
G2_ORDER
G1_ORDER
G0_ORDER
VID_ORDER
R/W-3h
R/W-2h
R/W-1h
R/W-0h
7
6
5
4
3
2
1
0
G_ORDER
Reserved
VID_EN
Reserved
GRPX0_EN
GRPX1_EN
GRPX2_EN
R/W-0h
R-0h
R/W-0h
R-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-142. COMP_sd_settings Register Field Descriptions
Bit
Field
Type
Reset
Description
31-17
Reserved
R
0h
Reserved
16
FB_SEL
R/W
0h
Feedback data selection: 0: select data from video alpha blending 1:
select data from final alpha blending
15-14
G2_ORDER
R/W
3h
Graphic2 layer display order when g_order = 1. From low to high: 00,
01, 10, and 11.
13-12
G1_ORDER
R/W
2h
Graphic1 layer display order when g_order = 1. From low to high: 00,
01, 10, and 11.
11-10
G0_ORDER
R/W
1h
Graphic0 layer display order when g_order = 1. From low to high: 00,
01, 10, and 11.
9-8
VID_ORDER
R/W
0h
Video layer display order. From low to high: 00, 01, 10, and 11.
7
G_ORDER
R/W
0h
Global reorder. 1: global reorder is on. The graphic layer priority is
based on g0_reorder, g1_reorder, g2_order
6
Reserved
R
0h
Reserved
5
VID_EN
R/W
0h
SD VID channel Enable 0 : Disabled 1 : Enabled
4-3
Reserved
R
0h
Reserved
2
GRPX0_EN
R/W
0h
GRPX0 channel enable 0 : Disabled 1 : Enabled
1
GRPX1_EN
R/W
0h
GRPX1 channel enable 0 : Disabled 1 : Enabled
0
GRPX2_EN
R/W
0h
GRPX2 channel enable 0 : Disabled 1 : Enabled