Registers
333
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.2.8
CIG_reg7 Register (offset = 1Ch) [reset = 0h]
CIG_reg7 is shown in
and described in
.
CIG PIP Position Config Reg
Figure 1-226. CIG_reg7 Register
31
30
29
28
27
26
25
24
Reserved
PIP_X
R-0h
R/W-0h
23
22
21
20
19
18
17
16
PIP_X
R/W-0h
15
14
13
12
11
10
9
8
Reserved
PIP_Y
R-0h
R/W-0h
7
6
5
4
3
2
1
0
PIP_Y
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-133. CIG_reg7 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-27
Reserved
R
0h
Reserved
26-16
PIP_X
R/W
0h
PIP window X position
15-11
Reserved
R
0h
Reserved
10-0
PIP_Y
R/W
0h
PIP window Y position