Texas Instruments DM38x DaVinci, Руководство пользователя

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Internal Modules
175 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.2.8.2.18.5 vblank and hblank Input Signals
Figure 1-125 shows the vblank from group1 and hblank from group2 signals being used. In this case, set
USE_ACTVID_HSYNC_N=’0’ and DISCRETE_BASIC_MODE=’0’. Again, since VIP is aware of the start
and end of vertical blanking interval start and end, vertical ancillary and active video data will appear in
different memory buffers. Lines starting from inactive to active transition on vblank will delineate a start of
the frame. When vblank is active, all data elements on pixel clock’s active edge will appear in ancillary
data buffer and when vblank is inactive, all data elements on pixel clock’s active edge will appear in video
data buffer.
Figure 1-125. vblank and hblank Input Signals
1.2.8.2.18.6 vblank and actvid Input Signals
Figure 1-126 shows vblank from Group 1 and actvid from Group 2 being used. Set
USE_ACTVID_HSYNC_N=’1’ and DISCRETE_BASIC_MODE=’0’. Again, since VIP is aware of the start
and end of vertical blanking interval start and end, vertical ancillary and active video data will appear in
different memory buffers. Lines starting from inactive to active transition on vblank will delineate a start of
the frame. When vblank and actvid are active, all data elements on pixel clock’s active edge will appear in
ancillary data buffer and when vblank is inactive and active is active, all data elements on pixel clock’s
active edge will appear in video data buffer.
Figure 1-126. vblank and actvid Input Signals