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DDR Timing Control and Software Leveling
21 SPRUIC7 – December 2016
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TMDSCSK388 Module Interface Details
3.4 DDR Timing Control and Software Leveling
Table 3-1 provides the calculated seed values. For more information about DDR3 leveling, refer to TI814x-
DDR3-Init-U-Boot .
Table 3-1. Calculated Seed Values
Parameters
DDR3 clock frequency 533 MHz
Invert Clkout 0
Trace Length (inches)
Byte 0 Byte 1 Byte 2 Byte 3
CK trace 1.8241295 1.8241295 1.3182095 1.3182095
DQS trace 0.7416985 0.5462986 0.9314172 0.6275384
Seed Values (per byte lane)
WR DQS 1A 1F 9 10
RD DQS 34 34 34 34
RD DQS GATE 85 7B 82 73
Seed Values to Input to Program
WR DQS 14
RD DQS 34
RD DQS GATE 7D
The following code snippet shows the optimum values obtained after running the
DDR3_SlaveRatio_ByteWiseSearch_TI814x.out file in CCS.
*********************************************************
BYTE3 BYTE2 BYTE1 BYTE0
*********************************************************
Read DQS MAX 6e 72 75 72
Read DQS MIN 2 7 9 6
Read DQS OPT 37 3c 3e 3d
*********************************************************
Read DQS GATE MAX 13c 13e 130 11e
Read DQS GATE MIN 0 0 0 0
Read DQS GATE OPT 99 9a 98 91
*********************************************************
Write DQS MAX a0 a0 94 9b
Write DQS MIN 0 0 0 0
Write DQS OPT 51 51 4a 4a
*********************************************************
Write DATA MAX bf bf bf c2
Write DATA MIN 4e 4c 4e 51
Write DATA OPT 88 88 87 8a
*********************************************************