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A

B

C

D

D

C

B

A

ti

6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA

TITLE

SHEET

OF

FILE

SIZE

DATE

REV

DRAWN BY

ENGINEER

REVISION HISTORY

REV

ENGINEERING CHANGE NUMBER

APPROVED

B

DATA ACQUISITION PRODUCTS

HIGH-PERFORMANCE ANALOG DIVISION

SEMICONDUCTOR GROUP

DOCUMENT CONTROL NO.

DAC8554EVM

A

6-Oct-2005

R. BENJAMIN

R. BENJAMIN

6457377

1

1

C:\WORK\DAC8554EVM\SCH\DAC8554 EVM.SCH

+5VA

SCLK

VSS

2

3

6

4

7

1

5

U2

OPA627AU

VCC

VCC

EXTERNAL

REFERENCE

1

2

3

R15

100K

1

2

3

R10 20K

VCC

VDD

VDD

VrefH

ENABLE

VSS

+REFin

+REFin

SDI

SCLK

SDI

VDD

-REFin

OUT_A

OUT_B

OUT_C

OUT_D

2

3

1

8

4

U4A
OPA2132UA

5

6

7

U4B

OPA2227UA

-REFin

VrefH

Vr

ef

H

VCC

U2_+IN

U2_-IN

U2_OUT

VrefL

VrefL

VCC = +15V Analog
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog

1

2

3

J1

1

2

3

J5

+5VA

NOTE:  Voltage range of -REFin input should not exceed
 0 - VrefH.

VCC

VSS

+5VA

-5VA

VDD

+3.3VD +1.8VD

+3.3VA

LDAC

SYNC

LDAC

ENABLE

A1

A0

A1

A0

SYNC

+3.3VA

AVDD

-VA

2

-5VA

4

AGND

6

VD1

8

+5VD

10

+VA

1

+5VA

3

DGND

5

+1.8VD

7

+3.3VD

9

J3

DAUGHTER-POWER

VoutB

2

IO_V/DVDD

12

LDAC

16

A1

14

GND

6

VrefH

3

VrefL

5

VoutA

1

ENABLE

15

A0

13

VoutD

8

Din

11

SCLK

10

SYNC

9

AVDD

4

VoutC

7

U1

DAC8554IPW

A0(+)

2

A1(+)

4

A2(+)

6

A3(+)

8

A4

10

A5

12

A6

14

A7

16

REF-

18

REF+

20

A0(-)

1

A1(-)

3

A2(-)

5

A3(-)

7

AGND

9

AGND

11

AGND

13

VCOM

15

AGND

17

AGND

19

J4

OUTPUT HEADER

GPIO0

2

DGND

4

GPIO1

6

GPIO2

8

DGND

10

GPIO3

12

GPIO4

14

SCL

16

DGND

18

SDA

20

CNTL

1

CLKX

3

CLKR

5

FSX

7

FSR

9

DX

11

DR

13

INT

15

TOUT

17

GPIO5

19

J2

DAUGHTER-SERIAL

R1

10K

R2

10K

R3

10K

R4

10K

R5

NI

R6

NI

C5

0.1uF

C2

10uF

1

2

3

JMP7

C7

0.1uF

C3

10uF

R11

0

R12

0

1

2

JMP2

1

2

JMP1

1

2

JMP4

1

2

JMP3

VIN

2

VOUT

6

TRIM

5

GND

4

TEMP

3

U3

REF02AU

C1
10uF

C4
0.1uF

TP1

REF OUT

R13

0

R16

20k

C6

0.1uF

1
2
3

JMP8

1

2

3

JMP9

TP4

AGND

TP3

TP2

TP5
+Vin
TP6

-Vin

R18
NI

R21

NI

R19 NI

R20 NI

R22

NI

R23

NI

R17

NI

C9

NI

C8

NI

R14

0

R7

10K

R9

10K

R8

10K

R24

100

C11

1uF

C10

1uF

C12

1nF

1

2

JMP5

1

2

JMP6

1

2

3

JMP10

1

2

3

JMP15

OPA IN

1

2

3

JMP16

OPA OUT

1
2
3

JMP11

OUT A

1
2
3

JMP12

OUT B

1
2
3

JMP13

OUT C

1
2
3

JMP14

OUT D

J4A (TOP) = SAM_TSM-110-01-L-DV-P
J4B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K 

J2A (TOP) = SAM_TSM-110-01-L-DV-P

J2B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K 

J3A (TOP) = SAM_TSM-105-01-L-DV-P

J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-K 

Содержание DAC8554EVM

Страница 1: ...sign and Performance 4 3 EVM Operation 14 4 Schematic 20 List of Figures 1 DAC8554EVM Functional Block Diagram 3 2 DAC8554EVM PCB Top Silkscreen Image 5 3 DAC8554EVM PCB Layer 1 Top Signal Layer 5 4 D...

Страница 2: ...l section are powered by 5V VDD The VCC supply source is primarily used to provide the positive rail of the external output op amp U2 the reference chip U3 and the reference buffer U4 The negative rai...

Страница 3: ...the trouble involved with building a custom cable Additionally there is also an MSP430 based platform HPA449 that uses the MSP430F449 microprocessor to which this EVM can connect and interface as wel...

Страница 4: ...ement and proper signal routing Place the bypass capacitors as close as possible to the device pins and properly separate the analog and digital signals from each other In the layout process carefully...

Страница 5: ...www ti com PCB Design and Performance Figure 2 DAC8554EVM PCB Top Silkscreen Image Figure 3 DAC8554EVM PCB Layer 1 Top Signal Layer SBAU121 January 2006 DAC8554EVM User s Guide 5...

Страница 6: ...www ti com PCB Design and Performance Figure 4 DAC8554EVM PCB Layer 2 Ground Plane Figure 5 DAC8554EVM PCB Layer 3 Power Plane DAC8554EVM User s Guide 6 SBAU121 January 2006...

Страница 7: ...www ti com PCB Design and Performance Figure 6 DAC8554EVM PCB Layer 4 Bottom Signal Layer Figure 7 DAC8554EVM PCB Bottom Silkscreen Image SBAU121 January 2006 DAC8554EVM User s Guide 7...

Страница 8: ...1 Minimum copper conductor width is 7 mils Minimum conductor spacing is 7 mils 12 Number of finished layers 4 13 Board dimensions 3 250 in x 1 7 in 50 15mil 0 381 mm PTH 43 23 622mil 0 6mm PTH 42 39 3...

Страница 9: ...www ti com PCB Design and Performance Figure 9 INL and DNL Characterization Graph of DAC A SBAU121 January 2006 DAC8554EVM User s Guide 9...

Страница 10: ...www ti com PCB Design and Performance Figure 10 INL and DNL Characterization Graph of DAC B DAC8554EVM User s Guide 10 SBAU121 January 2006...

Страница 11: ...www ti com PCB Design and Performance Figure 11 INL and DNL Characterization Graph of DAC C SBAU121 January 2006 DAC8554EVM User s Guide 11...

Страница 12: ...www ti com PCB Design and Performance Figure 12 INL and DNL Characterization Graph of DAC D 12 DAC8554EVM User s Guide SBAU121 January 2006...

Страница 13: ...05 X7R 10 3 C1 C2 C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor 10 F 1206 X7R Not 2 C8 C9 TDK Multilayer Ceramic Capacitor 1206 Installed 16 bit Quad Voltage Output Serial Input DAC 11 1 U1 Texas...

Страница 14: ...4 1 is connected to the noninverting input of the output op amp U2 JMP16 1 2 J4 5 is connected to the output of the op amp U2 The host processor drives the DAC Thus proper DAC operation depends on a s...

Страница 15: ...channels when stacking two EVMs together The DAC8554EVM includes an optional signal conditioning circuit for the DAC output through an external operational amplifier U2 The output op amp is set to uni...

Страница 16: ...pen resistor R9 3 4 2 Output Gain of 2 There are two types of configurations that will yield an output gain of 2 depending on the setup of jumpers JMP5 and JMP6 These configurations allow the user to...

Страница 17: ...U4 is used for reference buffering U4A while the other half is unused This unused op amp U4B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the re...

Страница 18: ...9 for output gain of 2 5V analog supply is selected for AVDD JMP7 3 3V analog supply is selected for AVDD Routes the adjustable buffered onboard 5V reference to the VREFH input of the DAC8554 JMP8 Rou...

Страница 19: ...Function Routes VOUTB to J4 4 JMP12 Routes VOUTB to J4 12 Routes VOUTC to J4 6 JMP13 Routes VOUTC to J4 14 Routes VOUTD to J4 8 JMP14 Routes VOUTD to J4 16 Routes J4 1 to U2 noninverting input JMP15 R...

Страница 20: ...www ti com 4 Schematic Schematic DAC8554EVM User s Guide 20 SBAU121 January 2006...

Страница 21: ...DVDD 12 LDAC 16 A1 14 GND 6 VrefH 3 VrefL 5 VoutA 1 ENABLE 15 A0 13 VoutD 8 Din 11 SCLK 10 SYNC 9 AVDD 4 VoutC 7 U1 DAC8554IPW A0 2 A1 4 A2 6 A3 8 A4 10 A5 12 A6 14 A7 16 REF 18 REF 20 A0 1 A1 3 A2 5...

Страница 22: ...proceeding User assumes all responsibility and liability for proper and safe handling and use of the EVM and the evaluation of the EVM TI shall have no liability for any costs losses or damages result...

Страница 23: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Страница 24: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments DAC8554EVM...

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