Texas Instruments DAC8534 Скачать руководство пользователя страница 21

EVM Stacking

3-3

EVM Operation

3.3

EVM Stacking

EVM stacking is possible if there is a need to evaluate two DAC8534 devices
in yielding a total of eight channel outputs. A maximum of two EVMs are
allowed, since the output terminal J4 dictates the number of DAC channels that
can be connected without colliding. Table 3 - 2 shows how the DAC output
channels are mapped into the output terminal J4, with respect to the jumper
position of W2, W11, W12, and W13.

Table 3 - 2. DAC Output Channel Mapping

Reference

Jumper Position

Function

1 - 2

DAC output A (V

OUT

A) is routed to J4 - 2.

W2

2 - 3

DAC output A (V

OUT

A) is routed to J4 - 10.

1 - 2

DAC output B (V

OUT

B) is routed to J4 - 4.

W11

2 - 3

DAC output B (V

OUT

B) is routed to J4 - 12.

1 - 2

DAC output C (V

OUT

C) is routed to J4 - 6.

W12

2 - 3

DAC output C (V

OUT

C) is routed to J4 - 14.

1 - 2

DAC output D (V

OUT

D) is routed to J4 - 8.

W13

2 - 3

DAC output D (V

OUT

D) is routed to J4 - 16.

In order to allow exclusive control of each stacked EVM, the DAC8534 must
have separate enable signals, EN. This is accomplished by routing the enable
signal of the first EVM through GPIO2 (P2/J2 pin 8), populating R27, and
disconnecting R28. The second EVM should use the GPIO3 (P2/J2 pin12) for
enable signal routing. Also, populate R28 and disconnect R27.

The LDAC signal can be shared to have a synchronous DAC output update.
If you prefer the LDAC signal be separated from each EVM, the same concept
described above should be implemented. Use GPIO0 and R25 for the first
EVM,  and GPIO1 and R26 for the second EVM.

3.4

The Output Op Amp

The EVM includes an optional signal conditioning circuit for the DAC output
through an external operational amplifier, U2. Only one DAC output channel
can be monitored at any given time for evaluation since the odd-numbered
pins (J4 - 1 to J4 - 15) are tied together. The output op amp is set to a gain of
2 configuration by default. Nevertheless, the raw outputs of the DAC can be
probed through the even-numbered pins of J4, the output terminal. This
header also provides mechanical stability when stacking, or plugging into any
interface card. In addition, it provides easy access for monitoring up to eight
DAC channels when stacking two EVMs together. See section 3.3.

The following sections describe the different configurations of the output
amplifier, U2.

Содержание DAC8534

Страница 1: ...DAC8534 Evaluation Module June 2003 Data Acqusition Digital Analog Converters User s Guide SLAU107...

Страница 2: ...itute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual p...

Страница 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Страница 4: ...here is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is design...

Страница 5: ...and circuit descriptions are included How to Use This Manual This document contains the following chapters Chapter 1 EVM Overview Chapter 2 PCB Design and Performance Chapter 3 EVM Operation Informati...

Страница 6: ...struments Data Converter evaluation modules please feel free to e mail the Data Converter Application Team at dataconvapps list ti com Include in the subject heading the product you have questions or...

Страница 7: ...ance 2 1 2 1 PCB Layout 2 2 2 2 EVM Performance 2 3 2 3 Bill of Materials 2 4 3 EVM Operation 3 1 3 1 Factory Default Setting 3 2 3 2 Host Processor Interface 3 2 3 3 EVM Stacking 3 3 3 4 The Output O...

Страница 8: ...2 2 2 5 Layer 4 Bottom Signal Plane 2 2 2 6 Bottom Silkscreen 2 2 2 7 Drill Drawing 2 2 Tables 2 1 Parts List 2 4 3 1 Factory Default Jumper Setting 3 2 3 2 DAC Output Channel Mapping 3 3 3 3 Unity Ga...

Страница 9: ...pter gives a general overview of the DAC8534 evaluation module EVM and describes some of the factors that must be considered in using this module Topic Page 1 1 Features 1 2 1 2 Power Requirements 1 2...

Страница 10: ...inals The device under test U1 can be powered by connecting an analog power supply at terminal 5 VA or 3 3 VA and selecting the proper position of jumper W1 This allows the DAC8534 analog section to o...

Страница 11: ...a host processor or waveform generator to the DAC8534 EVM using a custom built cable A specific adapter interface card is also available for most of TI s DSP starter kits DSK card models depend on the...

Страница 12: ...dule Output Buffer Module VCC VSS VCC GND GND VDD DAC Out 4 CH J1 J5 J6 P6 External Reference Module VDD J2 P2 A0 A1 SYNC SCLK LDAC TP2 W4 TP1 VSS DIN W2 W11 W12 W13 J4 P4 8 CH TP3 EN A0 A1 TP5 W6 W8...

Страница 13: ...bes the layout design and mechanical characteristics of the PCB as well as a brief description of the EVM test performance procedure The EVM bill of materials is also included in this section Topic Pa...

Страница 14: ...arated from each other The power and ground plane is very important and should be carefully considered in the layout process A solid plane is ideally preferred but sometimes impractical so when solid...

Страница 15: ...PCB Layout 2 3 PCB Design and Performance Figure 2 1 Top Silkscreen Figure 2 2 Layer 1 Top Signal Plane Figure 2 3 Layer Two Ground Plane...

Страница 16: ...PCB Layout 2 4 Figure 2 4 Layer 3 Power Plane Figure 2 5 Layer 4 Bottom Signal Plane Figure 2 6 Bottom Silkscreen...

Страница 17: ...using a high density DAC bench test board an Agilent 3458A digital multimeter and a PC running the LABVIEW software The EVM board is tested for all codes of 65535 and the device under test DUT is allo...

Страница 18: ...TSM 105 01 T DV 5X2X0 1 10 pin 3A isolated power socket 13 2 J2 J4 Samtec TSM 110 01 S DV M 10X2X 1 20 Pin 0 025 sq SMT socket 14 2 J1 J5 On Shore Technology ED555 3DS 3 Pin terminal connector 15 1 U1...

Страница 19: ...r to the DAC8534 data sheet SBAS254 for information about its serial interface and other related topics The EVM board is factory tested and configured to operate in the bipolar output mode Topic Page...

Страница 20: ...ut op amp U2 is configured for a gain of 2 J4 2 1 DAC output A VOUTA is connected to the noninverting input of the output op amp U2 3 2 Host Processor Interface The host processor basically drives the...

Страница 21: ...ignal of the first EVM through GPIO2 P2 J2 pin 8 populating R27 and disconnecting R28 The second EVM should use the GPIO3 P2 J2 pin12 for enable signal routing Also populate R28 and disconnect R27 The...

Страница 22: ...REFH as an offset or not Table 3 4 shows the proper jumper settings of the EVM for the 2 gain output of the DAC Table 3 4 Gain of Two Output Jumper Settings Jumper Setting Reference Unipolar Bipolar F...

Страница 23: ...ual package op amp OPA2132 U8 is used for reference buffering U8A while the other is unused This unused op amp U8B is available for whatever op amp circuit application the user desires to implement Th...

Страница 24: ...e supply rail of the output op amp U2 is powered by VSS for bipolar operation W5 1 3 Negative supply rail of the output op amp U2 is tied to AGND for unipolar operation 1 3 VREFL is tied to AGND W6 1...

Страница 25: ...2 1 3 Routes VOUTC to J4 14 1 3 Routes VOUTD to J4 8 W13 1 3 Routes VOUTD to J4 16 Disconnects the inverting input of the output op amp U2 from AGND W15 Connects the inverting input of the output op a...

Страница 26: ...Schematic 3 8 3 7 Schematic A 17 X11 schematic diagram is an attachment to this document...

Страница 27: ...AC SYNC 9 AVDD 4 VoutC 7 U1 DAC7574 8534 8574 VDD R15 440 0 R16 440 0 R5 3K R7 3K R1 10K R2 10K R3 10K R4 10K REFin W2 OUT_A1 OUT_C1 OUT_B1 OUT_D1 OUT_A2 OUT_B2 OUT_C2 OUT_D2 OUT_A OUT_B OUT_C OUT_D 2...

Отзывы: