RAM Control Module Registers
463
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
Internal Memory
5.2.2.21 Non-Master DMA Write Access Violation Address Register (MNMDMAWRAVADDR)
Figure 5-36. Non-Master DMA Write Access Violation Address Register (MNMDMAWRAVADDR)
31
0
NMDMAWRAVADDR
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 5-41. Non-Master DMA Write Access Violation Address Register (MNMDMAWRAVADDR)
Field Descriptions
Bit
Field
Value
Description
31-0
NMDMAWRAVADDR
Non-Master DMA Write Access Violation Address
This holds the address at which M3 µDMA attempted a write access and the non-master
DMA write access violation occurred.
5.2.2.22 Non-Master CPU Fetch Access Violation Address Register (MNMFAVADDR)
Figure 5-37. Non-Master CPU Fetch Access Violation Address Register (MNMFAVADDR)
31
0
NMCPUFAVADDR
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 5-42. Non-Master CPU Fetch Access Violation Address Register (MNMFAVADDR) Field
Descriptions
Bit
Field
Value
Description
31-0
NMCPUFAVADDR
Non-Master CPU Fetch Access Violation Address
This holds the address at which M3 CPU attempted a code fetch and the non-master
CPU fetch access violation occurred.
5.2.2.23 Master CPU Write Access Violation Address Register (MMWRAVADDR)
Figure 5-38. Master CPU Write Access Violation Address Register (MMWRAVADDR)
31
0
MCPUWRAVADDR
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 5-43. Master CPU Write Access Violation Address Register (MMWRAVADDR) Field
Descriptions
Bit
Field
Value
Description
31-0
MCPUWRAVADDR
Master CPU Write Access Violation Address
This holds the address at which M3 CPU attempted a write access and the master CPU
write access violation occurred.