Texas Instruments CC400DK, Руководство пользователя, Страница: 6 / 22

CC400DK Development kit (rev. 1.5) 2002-09-17 Page 6 of 22
The LOCK signal
A LOCK signal is connected to the parallel port interface to be monitored by the software. The
signal tells you if the synthesiser frequency is in lock. It is also available at a test pin, TP2,
and is active high.
NOTE: If Power Down mode is selected when the LOCK signal is high, the current
consumption will be approximately 23 uA. This is due to the current flowing from the LOCK
pin into the external buffer transistor (Q2). This transistor could be replaced with a MOSFET
to avoid this trickle current. Without this extra load the CC400 Power Down current is less
than 1 uA.
The modulation input/output
The modulation input/output (DIO) is connected to a separate connector. The connector type
is SMA female. The data to be sent has to be Manchester encoded (also known as bi-phase-
level coding). The Manchester code ensures that the signal has no DC component, which is
necessary for the FSK demodulator. The Manchester code is based on transitions; a “0” is
encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition. See figure
below. Maximum data-rate is 9.6 kbit/s and is chosen in the software. To test your module
use a 3V
pp
logic level with 1-10 kHz square wave.
Time
TX
data
1 0 1 1 0 0 0 1 1 0 1
LNA/PA matching
The input/output matching network is optimised for 433.92MHz operation. The component
values are calculated in the software program, and consist of C51, C61, L51 and L61. Using
the specified component values for the input/output match will give an optimum match at the
specified operating frequency. Minor tuning of the component values may be necessary to
compensate for layout parasitics at other frequencies or other layouts. See appendix A.