Copyright © 2019, Texas Instruments Incorporated
Terminal Configuration and Functions
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SWRS224A – FEBRUARY 2019 – REVISED AUGUST 2019
Table 4-2. Pin Attributes and Pin Multiplexing (continued)
GENERAL PIN ATTRIBUTES
FUNCTION
PAD STATES
Pkg.
Pin
Pin Alias
Use
Select as
Wakeup
Source
Config.
Addl.
Analog
Mux
Muxed
With
JTAG
Dig. Pin Mux
Config. Reg.
Dig.
Pin
Mux
Config.
Mode
Value
Signal Name
Signal
Description
Signal
Direction
LPDS
Hib
nRESET = 0
54
GPIO9
I/O
No
No
No
GPIO_PAD_
CONFIG_9
(0x4402 E0C4)
0
GPIO9
GPIO
I/O
Hi-Z,
Pull,
Drive
Hi-Z,
Pull,
Drive
Hi-Z
3
GT_PWM05
Pulse-width
modulated O/P
O
6
SDCARD_
DATA0
SD card data
I/O
7
McAXR0
I2S audio port data
(RX, TX)
I/O
12
GT_CCP00
Timer capture port
I
55
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
56
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
57
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
58
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
59
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
60
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
61
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
62
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
63
GND
GND
N/A
N/A
N/A
N/A
N/A
GND
GND
N/A
N/A
N/A
N/A
(1) LPDS state: The state of unused I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(2) Hibernate mode: The state of the I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(3) To minimize leakage in some serial Flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldowns on FLASH_SPI_DIN,
FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(4) Pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During
hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.
(5) For details on proper use, see
Drive Strength and Reset States for Analog-Digital Multiplexed Pins
.
(6) Pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the chip hardware power-up mode. For this reason, the pin must be output only when used
for digital functions.
(7) Device firmware automatically enables the digital path during ROM boot.
(8) Requires user configuration to enable the analog switch of the ADC channel. (Switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the
ADC switch.
(9) Pin is shared by the ADC inputs and digital I/O pad cells.