Texas Instruments CC2533, Руководство пользователя

Страница: 77 / 370

www.ti.com
Flash Write
6.2.2 Writing Multiple Times to a Word
The following rules apply when writing multiple times to a 32-bit word between erase:
• Writing 0 to a bit within a 32-bit flash word, which has been set to 1 by the last erase operation,
changes the state of the bit to 0, subject to the last bullet below.
• It is possible to write 0 to a bit within a 32-bit word repeatedly (subject to the last bullet below) once the
bit has been written with 0. This does not change the state of the bit.
•
Writing 1 to a bit does not change the state of the bit, subject to the last bullet below.
• The following limitations apply to writes subsequent to the last page erase:
– A 0 must not be written more than two times to a single bit.
– A 32-bit word shall not be written more than 8 times.
– A page must not be written more than 1024 times.
The state of any bit of a 32-bit flash word is nondeterministic if these limitations are violated.
This makes it possible to write up to 4 new bits to a 32-bit word 8 times. One example write sequence to a
word is shown in
Table 6-1 . Here b
n
represents the 4 new bits written to the word for each update. This
technique is useful to maximize the lifetime of the flash for data-logging applications.
Table 6-1. Example Write Sequence
Step Value Written FLASH Contents After Writing Comment
1 (page erase) 0xFFFFFFFF The erase sets all bits to 1.
Only the bits written 0 are set to 0, whereas all bits
2 0xFFFFFFFb
0
0xFFFFFFFb
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
3 0xFFFFFFb
1
F 0xFFFFFFb
1
b
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
4 0xFFFFFb
2
FF 0xFFFFFb
2
b
1
b
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
5 0xFFFFb
3
FFF 0xFFFFb
3
b
2
b
1
b
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
6 0xFFFb
4
FFFF 0xFFFb
4
b
3
b
2
b
1
b
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
7 0xFFb
5
FFFFF 0xFFb
5
b
4
b
3
b
2
b
1
b
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
8 0xFb
6
FFFFFF 0xFb
6
b
5
b
4
b
3
b
2
b
1
b
0
written 1 are ignored.
Only the bits written 0 are set to 0, whereas all bits
9 0xb
7
FFFFFFF 0xb
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
written 1 are ignored.
6.2.3 DMA Flash Write
When using DMA write operations, the data to be written into flash is stored in the XDATA memory space
(RAM or registers). A DMA channel is configured to read the data to be written from the memory source
address and write this data to the flash write-data register (
FWDATA
) fixed destination address, with the
DMA trigger event
FLASH
(
TRIG[4:0]
= 1 0010 in DMA configuration) enabled. Thus, the flash controller
triggers a DMA transfer when the flash write-data register,
FWDATA
, is ready to receive new data. The
DMA channel should be configured to perform single-mode, byte-size transfers with the source address
set to start-of-data block and destination address to fixed
FWDATA
(note that the block size,
LEN
in
configuration data, must be divisible by 4; otherwise, the last word is not written to the flash). High priority
should also be ensured for the DMA channel, so it is not interrupted in the write process. If interrupted for
more than 20
μ
s, the write operation may time out, and the write bit,
FCTL.WRITE
, is set to 0.
When the DMA channel is armed, starting a flash write by setting
FCTL.WRITE
to 1 triggers the first DMA
transfer (DMA and flash controller handle the reset of the transfer).
Figure 6-1 shows an example of how a DMA channel is configured and how a DMA transfer is initiated to
write a block of data from a location in XDATA to flash memory.
77 SWRU191C – April 2009 – Revised January 2012 Flash Controller
Submit Documentation Feedback
Copyright © 2009 – 2012, Texas Instruments Incorporated