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Antenna Diversity Patch
5 SWRA523B – September 2016 – Revised March 2017
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CC13xx Antenna Diversity
2.5 Configuration Registers
Table 3 lists the configuration registers available in the antenna diversity patch.
Table 3. Configuration Registers
Register Bits Name Description Default
0x4004 52B0
15–8 PreTimeout PreTimeout_bits = PreT 8 0x02
7–0 SyncTimeout SyncTimeout_bits = Sy Pre SyncTimeout – 31 0x18
0x4004 52B4
15 NA NA 0x00
14 CsQual Carrier sense qualified preamble 0x01
13–12 NA NA 0x00
11–8 PreLen
Number of preamble bits for correlation
PreLen_bits = 1
0x07
7–0 PreThr Preamble correlation threshold 0x0B
0x4004 6088 15–0 AgcRssiRef
AGC RSSI reference level for gain adjustment
AgcRssiRef_dBm = AgcRssiRef – 2
16
[dBm]
0xFFA6
0x4004 6090
15–8 Reserved 0x0A
7–0 CS_THR
Carrier sense threshold
CS_THR_dBm = CS_THR – 256 [dBm]
0x91
This register can only be changed by static overrides of the following format:
HW_REG_OVERRIDE( 0xXXXX , 0xYYYY ),
where:
• XXXX is the 2 least significant bytes of the register address (52B0, 52B4, 6088, or 6090)
• YYYY is the value to write
As an example, the following register write sets the carrier sense threshold to –111 dBm:
HW_REG_OVERRIDE( 0x6090 , 0x0A91 ),
Increasing the carrier threshold to –107 dBm (for example) yields the following:
HW_REG_OVERRIDE( 0x6090 , 0x0A95 ),
2.6 Status Registers
Table 4 lists the status registers available in the antenna diversity patch.
Table 4. Status Registers
Register Bits Name Description Default
0x4004 5178 15–0 AntSelect
Antenna selection TX and RX
0: Antenna0
1: Antenna1
0x00
0x4004 517C
15–8 RSSI1 RSSI antenna 1 0x00
7–0 RSSI0 RSSI antenna 0 0x00
0x4004 51C8 11–0 AntSelect0Cnt Antenna select 0 counter 0x00
0x4004 51CC 11–0 AntSelect1Cnt Antenna select 1 counter 0x00
In TX, the AntSelect selects the antenna that is used for the transmission. The configuration registers do
not have retention, so if the RF Core is power cycled, the application must then update the AntSelect
register. The ARM
®
Cortex
®
-M3 processor must read the register value before power cycling the RF Core,
and then the processor must write the register value again before entering TX.
The registers can be read using the CMD_READ_RFREG API command but can be written only as an
override (when doing a CMD_PROP_RADIO_DIV_SETUP).