5.4 Schematic
through
illustrate the schematics.
2P
1P
1N
4P
3P
BAT
VSS
VSS
VSS
VSS
GND
SRP
SRN
6P
5P
TP14
100
R21
100
R22
TP12
0.001
R24
t
°
RT1
VC6
VC5
VC4
VC3
VC2
VC1
SRP
SRN
PACK
DSG
PCHG
CHG
FUSE
NT1
Net-Tie
7P
100
R1
TP18
TP19
BAT-
GND
TP2
VSS
PDSG
VC0
VC7
REG1
2.2uF
C19
BAT-
1P
2P
3P
4P
5P
6P
TP5
TP10
VSS
GND
TP15
0.47uF
C3
4
1
3
2
S1
0
R13
DNP
VSS
GND
TP16
VSS
GND
TP17
PGND
LD
1
2
3
J6
10k
R23
TP11
TS1
TS2
20.0
R2
20.0
R5
CHG
DSG
PACK
LD
PCHG
PDSG
FUSE
VSS
VSS
10k
R18
TP13
TP4
VSS
TP6
REG1
VSS
Input
45V 10A
7P
CD
WAKE
4
1
3
2
S2
RESET
TP3
BREG
REGIN
REG18
VC10
VC9
VC8
20.0
R9
20.0
R6
20.0
R10
20.0
R11
20.0
R12
20.0
R14
20.0
R15
20.0
R16
20.0
R17
9P
8P
10P
8P
9P
t
°
RT2
VSS
VSS
TP9
REG2
VSS
CFETOFF
HDQ
ALERT
SDA
SCL
TS2
REGIN
REG1
VSS
VSS
REG1
DFETOFF
DDSG
DCHG
VSS
VSS
DDSG
DCHG
DFETOFF
EXTTS2
1
2
3
J5
10k
R19
REG1
VSS
TP1
DNP
TP8
DNP
RST_SHUT
5
4
1
2
3
6
J4
EXTTS2
RST_SHUT
CFETOFF
CFETOFF
CFETOFF
0.01uF
C17
1uF
C10
0.1uF
C22
5
4
1
2
3
J2
REG2
REG2
BAT+
100k
R20
100V
D1
1
3
2
,4 Q1
FCX495TA
1uF
C13
1
2
3
4
5
1
2
3
4
5
J1
1
2
3
4
5
6
1
2
3
4
5
6
J3
LD
41
VC1
15
SDA
27
VC10
48
CHG
45
VC3
13
NC
11
NC
9
NC
7
NC
5
NC
3
NC
1
FUSE
38
BREG
37
REG18
24
HDQ
28
SCL
26
ALERT
25
VC0
16
VSS
17
SRP
18
NC
19
SRN
20
NC
44
TS1
21
TS2
22
TS3
23
DSG
43
BAT
47
CFETOFF
29
DFETOFF
30
DCHG
31
DDSG
32
RST_SHUT
33
REG2
34
REG1
35
REGIN
36
PACK
42
PDSG
39
PCHG
40
VC2
14
VC4
12
VC5
10
VC6
8
VC7
6
VC8
4
VC9
2
CP1
46
BQ76942PFBR
U1
10P
TS2
150
R3
150
R7
150
R4
DNP
150
R8
DNP
100V
D2
1uF
C1
VSS
100pF
C2
0.01uF
C20
DNP
100pF
C21
TP7
VSS
1uF
C57
22nF
C11
220nF
C9
220nF
C12
220nF
C8
220nF
C7
220nF
C14
220nF
C15
220nF
C18
220nF
C16
220nF
C4
220nF
C5
220nF
C6
Figure 5-9. Schematic Diagram Monitor
BQ76942EVM Circuit Module Physical Construction
SLUUC32A – NOVEMBER 2019 – REVISED OCTOBER 2020
BQ76942 Evaluation Module
39
Copyright © 2020 Texas Instruments Incorporated