Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
LOW
1.3
µs
t
HIGH
High period of the SCL clock
600
ns
t
SU:STA
Setup repeated START
600
ns
t
HD:DAT
Data hold time (SDA input)
0
ns
t
SU:DAT
100
ns
t
r
Clock rise time
10% to 90%
300
ns
t
f
Clock fall time
90% to 10%
300
ns
t
SU:STO
Setup time STOP condition
0.6
µs
t
BUF
Bus free time STOP to START
1.3
µs
t
RST
I
2
C bus reset
Bus interface is reset if SCL is detected
low for this duration
1.9
2.1
s
R
PULLUP
Pullup resistor
Pullup voltage rail ≤ 5 V
1.5
kΩ
(1)
Operation with V
BAT
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
5.5 V or 11 V mode), the maximum voltage on V
BAT
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
their maximum specified voltage.
(2)
Specified by design
(3)
Specified by characterization
7.29 Timing Requirements - HDQ Interface
Typical values stated where T
A
= 25°C and V
BAT
= 59.2 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 80 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
B
Break Time
190
µs
t
BR
Break Recovery Time
40
µs
t
HW1
Host Write 1 Time
Host drives HDQ
0.5
50
µs
t
HW0
Host Write 0 Time
Host drives HDQ
86
145
µs
t
CYCH
Cycle Time, Host to device
Device drives HDQ
190
µs
t
CYCD
Cycle Time, device to Host
Device drives HDQ
190
205
250
µs
t
DW1
Device Write 1 Time
Device drives HDQ
32
50
µs
t
DW0
Device Write 0 Time
Device drives HDQ
80
145
µs
t
RSPS
Device Response Time
Device drives HDQ
190
µs
t
TRND
Host Turn Around Time
Host drives HDQ after device drives HDQ
210
µs
t
RISE
HDQ Line Rising Time to Logic 1
1.8
µs
t
RST
Host holds bus low to initiate device
interface reset
1.9
2.1
s
R
PULLUP
Pullup Resistor
Pullup voltage rail ≤ 5 V
1.5
kΩ
(1)
Operation with V
BAT
up to 80 V is supported when the charge pump is not in operation. Whenever the charge pump is in operation (in
5.5 V or 11 V mode), the maximum voltage on V
BAT
should be reduced to ensure the voltage on CP1, CHG, and DSG does not exceed
their maximum specified voltage.
(2)
Specified by design
(3)
Specified by characterization
(4)
Response time will vary depending on the internal device processing
SLUSE91A – SEPTEMBER 2020 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated
23
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