Test Summary
8
SLUUC12 – February 2019
Copyright © 2019, Texas Instruments Incorporated
BQ25887 QFN boost-mode battery charger with cell balancing evaluation
module
Advance Information
2.3
Helpful Tips
The following list provides a few helpful tips:
•
The leads and cables to the various power supplies, batteries, and loads have resistance. The current
meters also have series resistance. The charger dynamically reduces charge current depending on the
voltage sensed at its VBUS pin (using the VINDPM feature), BAT pin (as part of normal termination),
and TS pin (through its battery temperature monitoring feature through the battery thermistor).
Therefore, the designer must use voltmeters to measure the voltage as close to the IC pins (TP7,
TP15, and TP16) as possible instead of relying on the digital readouts of the power supply.
•
When using a source meter that can source and sink current as the battery simulator, TI highly
recommends adding two large capacitors (1000uF or greater) at BAT, TOP-/BOT+, and GND
connectors to prevent oscillations at the BAT pin, which are due to mismatched impedances of the
charger output and source meter input within their respective regulation loop bandwidths. Configuring
the source meter for four-wire sensing eliminates the requirement for a separate voltmeter to measure
the voltage at the BAT pin. When using four-wire sensing, always ensure that the sensing leads are
connected to prevent accidental overvoltage by the power supply.
•
For precise measurements of efficiency and charge current or battery regulation (or both) near
termination, a current meter in series with the battery or battery simulator must not be set to auto-range
and may require removal, entirely. This EVM offers an alternate method for measuring currents by
measuring the voltage across a 1%, thermally-capable (for example, 0.010
Ω
in a 1210 or larger
footprint) resistor in series between the power sources and power pins.
3
PCB Layout Guidelines
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components that minimize the high-frequency current path loop is important to prevent electrical and
magnetic field radiation and high-frequency resonant problems. To ensure proper layout, follow the priority
list for this printed-circuit board (PCB) in the order presented:
1. Place the output capacitor as close as possible to the SYS or SNS pin and GND pin connections and
use the shortest copper trace connection or GND plane.
2. Put the input capacitors near to the VBUS and PMID pins. Tie ground connections to the IC ground
with a short copper trace connection or GND plane.
3. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using the power pad as the
single ground connection point or use a 0-
Ω
resistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. One critical note regarding the layout is that the exposed power pad on the backside of the IC package
must be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC
connecting to the ground plane on the other layers.
8. The via size and number must be sufficient for a given current path.
See the EVM design for the recommended component placement with trace and via locations..
