Texas Instruments BQ25306EVM, Руководство пользователя

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1. Place the input capacitor as close as possible to the PMID pin and GND pin connections and use the shortest
copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this trace to
lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do
not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any
other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a short
copper trace connection or GND plane.
4. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
5. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other
layers.
6. The via size and number should be enough for a given current path.
7. For more layout guidelines and recommendations refer to the datasheet of the respective battery charger IC
8. See the EVM design for the recommended component placement with trace and via locations. For the QFN
information, refer to Quad Flatpack No-Lead Logic Packages Application Report and QFN and SON PCB
Attachment Application Report .
4 Board Layout, Schematic, and Bill of Materials
4.1 Board Layout
The board layout is shown in Figure 4-1 to Figure 4-6 .
Figure 4-1. Top Overlay
Figure 4-2. Top Solder
Board Layout, Schematic, and Bill of Materials www.ti.com
6 BQ25306 (BMS005) Evaluation Module SLUUC50A – MARCH 2020 – REVISED DECEMBER 2020
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