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Table 9-7. Inductor Series (continued)

INDUCTANCE (µH)

DCR (Ω)

DIMENSIONS

(mm

3

)

INDUCTOR TYPE

COMMENT

2.2

0.12

2.5 x 2.0 x 1.2

MIPSA2520 2R2

TDK

2.2

0.145

3.3 x 3.3 x 1.4

LPS3314

Coicraft

(1)

See

Third-Party Products Disclaimer

The PWM allows the use of small ceramic capacitors. Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. At
light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value and the PFM peak inductor current. Because the PWM converter has a pulsating input
current, a low ESR input capacitor is required on PMID for the best voltage filtering to ensure proper function of
the device and to minimize input voltage spikes. For most applications a 10-µF capacitor value is sufficient. The
PMID capacitor can be increased to 22 µF for better input voltage filtering.

shows the recommended input/output capacitors.

Table 9-8. Capacitors

CAPACITANCE (µF)

SIZE

CAPACITOR TYPE

COMMENT

10

0603

GRM188R60J106ME84

Murata

Recommended

10

0402

CL05A106MP5NUNC

Samsung EMA

Smallest size

(1)

See

Third-Party Products Disclaimer

9.3.22 Load Switch / LDO Output and Control

The device integrates a low Iq load switch which can also be used as a regulated output. The LSCTRL pin can
be used to turn the load on or off. Activating LSCTRL continuously holds the switch in the on state so long as
there is not a fault. The signal is active HI and has a low threshold making it capable of interfacing with low
voltage signals. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to
VINLS. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times
larger than the output capacitor on LS/LDO.

The output voltage is programmable using the LS_LDO bits in the register. The LS/LDO voltage is calculated
using

LS/LDO = 0.8 V + LS_LDOCODE x 100 mV

(9)

If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS -
V

(DROPOUT)

summarizes the control of the LS/LDO output based on the I

2

C or LSCTRL pin setting:

Table 9-9. LS/LDO Output Control

I

2

C LS_LDO_EN

PIN LSCTRL

I

2

C V

LDO

> 3.3

LS/LDO OUTPUT

0

0

0

Pulldown

0

0

1

Pulldown

0

1

0

V

LDO

0

1

1

LSW

1

0

0

V

LDO

1

0

1

LSW

1

1

0

V

LDO

1

1

1

LSW

If the output of the LDO is less than the programmed V

(SYS)

voltage, connect VINLS to SYS. If the output of the

LDO is greater than the programmed V

SYS

voltage, connect VINLS to PMID.

SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021

28

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Copyright © 2022 Texas Instruments Incorporated

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Содержание BQ25120F3A

Страница 1: ...and current Termination threshold Input current limit VINDPM Threshold Timer options Load switch control System output voltage adjustment LDO output voltage adjustment 2 Applications Smart watches an...

Страница 2: ...pplication Information 48 10 2 Typical Application 49 11 Power Supply Recommendations 64 12 Layout 65 12 1 Layout Guidelines 65 12 2 Layout Example 65 13 Device and Documentation Support 66 13 1 Devic...

Страница 3: ...th timer allows multiple different configuration options for wake are reset optimization A simple voltage based monitor provides battery level information to the host in 2 increments from 60 to 100 of...

Страница 4: ...nly is present and disable charge when VIN is present CD is pulled low internally with 900 k SDA E4 I O I2C Interface Data Connect SDA to the logic rail through a 10 k resistor SCL E5 I I2C Interface...

Страница 5: ...c voltage rail using a 1k to 100k resistor RESET D3 O Reset Output RESET is an open drain active low output that goes low when MR is held low for longer than tRESET which is configurable by the MRRESE...

Страница 6: ...V Charged device model CDM per JEDEC specification JESD22 C101 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP15...

Страница 7: ...aracterization parameter 1 2 C W JB Junction to board characterization parameter 12 0 C W R JC bot Junction to case bottom thermal resistance N A C W 1 For more information about traditional and new t...

Страница 8: ...MENT and INPUT CURRENT LIMIT VDO IN PMID VIN V PMID VIN 5 V IIN 300 mA 125 170 mV VDO BAT PMID V BAT V PMID VIN 0 V V BAT 3 V Iff 400 mA 120 160 mV V BSUP1 Enter supplement mode threshold V BAT V BUVL...

Страница 9: ..._HS PMID 3 6 V I SYS 150 mA 675 850 m RDS ON_LS PMID 3 6 V I SYS 150 mA 300 475 m RDS CH_SYS MOSFET on resistance for SYS discharge VIN 3 6 V IOUT 10 mA into VOUT pin 22 40 I LIMF SW Current limit HS...

Страница 10: ...ure threshold VTS rising 1 VIN Hysteresis 35 4 36 36 4 VIN VCOLD Low temperature threshold VTS rising 1 VIN Hysteresis 39 3 39 8 40 2 VIN TSOFF TS Disable threshold VTS rising 2 VIN Hysteresis 55 60 V...

Страница 11: ...1 V 0 275 V IBIAS High Level leakage current VPULLUP 1 8 V SDA and SCL 1 A INT PG and RESET OUTPUT Open Drain VOL Low level output threshold Sinking current 5 mA 0 25 x V SYS V IIN Bias current into p...

Страница 12: ...s LS LDO OUTPUT tON_LDO Turn ON time 100 mA load 500 s tOFF_LDO Turn OFF time 100 mA load 5 s PUSHBUTTON TIMER tWAKE1 Push button timer wake 1 Programmable Range for wake1 function 0 08 1 s tWAKE2 Pus...

Страница 13: ...Typical Start Up Timing and Operation VBAT VBUVLO Remove Battery Shows Charge Status VISET 3uA max 4uA max No SYS Load SYS Load Applied 3uA max 5uA max 4uA max nA of leakage with VIN present 0mA Cond...

Страница 14: ...d up to SYS ISYS 10 A EN_INT 1 Figure 8 2 Battery Operation and Sleep Mode BQ25120F3A SLUSDI4A OCTOBER 2018 REVISED APRIL 2021 www ti com 14 Submit Document Feedback Copyright 2022 Texas Instruments I...

Страница 15: ...qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 D024 Figure 8 6 Blocking FET RDS ON vs Temperature Temperature qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 50 1...

Страница 16: ...re Charge Current Temperature qC R DS ON m 40 25 10 5 20 35 50 65 80 95 110 125 0 100 200 300 400 500 600 700 800 900 1000 D026 D024 VIN 5 V Figure 8 12 RDS ON of High Side MOSFET vs Temperature Tempe...

Страница 17: ...L SYS 1C 0 5C Disable Disable VBATREG 140mV LDO Load Switch Control IINLIM Q1 Q2 Q3 Q4 VIN_DPM VSUPPLY VBATREG LDO Control VSYSREG Thermal Shutdown Termination Reference IBAT VIN VINOVP VBAT VBATOVP V...

Страница 18: ...t the device will enter Ship Mode upon removal of the supply The EN_SHIPMODE bit can be cleared using the I2C interface as well while the IN input is valid In addition to VIN VUVLO CD and MR must be h...

Страница 19: ...rge Disabled 9 3 3 Active Battery Only Connected When the battery above VBATUVLO is connected with no input source the battery discharge FET is turned on After the battery rises above VBATUVLO and the...

Страница 20: ...VBMON 94 or 96 VBMON 90 or 92 VBMON 86 or 88 VBMON 84 D E C O D E R S3 S2 S1 S0 2 BAT TAP 4 BAT TAP 6 BAT TAP 8 BAT TAP 10 BAT TAP VREF 90 VB 80 VB 70 VB 60 VB VB 0 8 VBAT VBGUAGE_TH 2 0 Figure 9 3 V...

Страница 21: ...n the control register determines whether a charge cycle is initiated When the CE bit is 1 and a valid input source is connected the battery discharge FET is turned off and the output at SYS is regula...

Страница 22: ...n external resistor or through registers over I2C Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND The termination can be set between 5 and 20 of the pr...

Страница 23: ...lly programmed value the voltage at ISET reflects the actual charging current and can be used to monitor charge current The current out of ISET is 1 100 10 of the charge current The charge current can...

Страница 24: ...TS input for monitoring the battery pack NTC thermistor The voltage at TS is monitored to determine that the battery is at a safe temperature during charging Three temperature thresholds are monitored...

Страница 25: ...hresholds are not independently programmable The cool and warm NTC resistances for a selected resistor divider are calculated using Equation 3 and Equation 4 COOL COOL COOL LO HI COOL LO LO HI R x R x...

Страница 26: ...as a MR shifted MRS output when the PGB_MRS bit is set to 1 PG is high impedance when the MR input is not low and PG pulls to GND when the MR input is below VOL TH_MRS Connect PG to the desired logic...

Страница 27: ...Pulse Frequency Modulation to lower the power consumed at low loads the output voltage ripple and the efficiency The selected inductor must be selected for its DC resistance and saturation current The...

Страница 28: ...evice integrates a low Iq load switch which can also be used as a regulated output The LSCTRL pin can be used to turn the load on or off Activating LSCTRL continuously holds the switch in the on state...

Страница 29: ...the host and the WAKE1 and or WAKE2 bits are updated on I2C The MR_WAKE bits and RESET FAULT bits are not cleared until the Push button Control Register is read from I2C When a MR reset condition is...

Страница 30: ...ult and Status Condition Responses FAULT or STATUS ACTIONS CHARGER BEHAVIOR SYS BEHAVIOR LS LDO BEHAVIOR TS BEHAVIOR VIN_OV Update VIN_OV status Update STAT to fault interrupt on INT PG shown not good...

Страница 31: ...fault event must be cleared before going to the previous state DONE The termination requirements have been met VBAT is monitored and Charging resumes when conditions are met RESET yVIN_OV yVIN_UV yOV...

Страница 32: ...ible interface to program and read many parameters I2C is a 2 wire serial interface developed by NXP The bus consists of a data line SDA and a clock line SCL with pull up structures When the bus is id...

Страница 33: ...ensures that data is valid A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse see Figure 9 8 All devices recognize the address sent by the mast...

Страница 34: ...sed slave All I2C compatible devices must recognize the STOP condition Upon the receipt of a STOP condition all devices know that the bus is released and wait for a START condition followed by a match...

Страница 35: ...s only B6 STAT_0 R x B5 EN_SHIPMODE Write Only 0 0 Normal Operation 1 Ship Mode Enabled B4 RESET_FAULT R x 1 RESET fault Indicates when the device meets the RESET conditions and is cleared after I2C r...

Страница 36: ...fault VIN_UV is set when the input falls below VSLP VIN_UV fault shows only one time Once read VIN_UV clears until another UVLO event occurs B5 BAT_UVLO R x 1 BAT_UVLO fault BAT_UVLO continues to show...

Страница 37: ...t 01 TS temp TCOLD or TS temp THOT Charging suspended 10 TCOOL TS temp TCOLD Charging current reduced by half 11 N A B5 TS_FAULT0 R x B4 Reserved R x Reserved B3 EN_INT R W 1 0 Disable INT function IN...

Страница 38: ...owing equation If ICHRG_RANGE is 0 then ICHRG 5 mA ICHRGCODE x 1 mA If ICHRG_RANGE is 1 then ICHRG 40 mA ICHRGCODE x 10 mA If a value greater than 35 mA ICHRG_RANGE 0 or 300 mA ICHRG_RANGE 1 is writte...

Страница 39: ...ollowing equation If IPRETERM_RANGE is 0 then ITERM 500 A ITERMCODE x 500 A If IPRETERM_RANGE is 1 then ITERM 6 mA ITERMCODE x 1 mA If a value greater than 5 mA IPRETERM_RANGE 0 is written the setting...

Страница 40: ...G is calculated using the following equation VBATREG 3 6 V VBREGCODE x 10 mV The charge voltage range is from 3 6 V to 4 65 V If a value greater than 4 65 V is written the setting goes to 4 65 V BQ251...

Страница 41: ...step if SYS_SEL is 01 or 11 B1 SYS_VOUT_0 R W 1 OUT Voltage 100 mV step if SYS_SEL is 01 or 11 B0 LSB 0 SW_VOUT Bits Use SYS_SEL and SYS_VOUT bits to set the output on SYS The SYS voltage is calculate...

Страница 42: ...V 10 0111 2 083 V 10 1000 2 167 V 10 1001 2 25 V 10 1010 2 333 V 10 1011 2 417 V 10 1100 2 5 V 10 1101 2 583 V 10 1110 2 667 V 10 1111 2 75 V 11 0000 1 8 V 11 0001 1 9 V 11 0010 2 V 11 0011 2 1 V 11 0...

Страница 43: ...LS_LDO_1 R W 1 LS LDO Voltage 200 mV B2 LS_LDO_0 R W 0 LS LDO Voltage 100 mV B1 0 B0 LSB MRRESET_VIN R W 0 0 Reset sent when MR Reset time is met 1 Reset sent when MR Reset time is met and VUVLO VSLP...

Страница 44: ...W 0 0 After Reset device enters Ship mode 1 After Reset device enters Hi Z Mode B4 MRRESET_1 R W 0 MR Timer adjustment for reset 00 5 s 20 01 9 s 20 10 11 s 20 11 15 s 20 B3 MRRESET_0 R W 0 B2 PGB_MR...

Страница 45: ...he following equation I INLIM 50 mA I INLIM CODE x 50 mA The default may be overridden by the external resistor on ILIM 9 6 11 Voltage Based Battery Monitor Register Memory location 0x0Ah Reset State...

Страница 46: ...hen it will move to VBMON_RANGE 10 80 to 90 and continue until a non 000 value of VBMON_TH is found If this does not happen then VBMON_RANGE and VBMON_TH will be written with 00 000 The VBMON_READ bit...

Страница 47: ...mV B5 VINDPM_1 R W 0 Input V IN_DPM voltage 200 mV B4 VINDPM_0 R W 0 Input V IN_DPM voltage 100 mV B3 2XTMR_EN R W 0 0 Timer is not slowed at any time 1 Timer is slowed by 2x when in any control other...

Страница 48: ...s for ILIM IPRETERM and ISET These are not needed if these values are set with a host controller through I2C commands This design also shows the TS resistors which is also optional When powering up in...

Страница 49: ...VINLS Unregulated Load PMID PG IPRETERM ISET ILIM CD IN 4 7 F 2 2 H 10 F 1 F 1 F 14 k 14 3 k 499 4 99 k 4 k 1 F Figure 10 1 Typical Application Circuit www ti com BQ25120F3A SLUSDI4A OCTOBER 2018 REV...

Страница 50: ...application diagram 10 2 2 1 Default Settings Connect ISET ILIM and IPRETERM pins to ground to program fast charge current to 40 mA input current limit to 100 mA and pre charge termination current to...

Страница 51: ...he voltage at TS is monitored to determine that the battery is at a safe temperature during charging Refer to Section 8 for the detailed thresholds number The TS circuit is shown in Figure 9 4 The res...

Страница 52: ...0 mV div Figure 10 4 Entering DPPM Mode Time 4 ms div 10 mA div 100 mA div 2 V div 500 mV div Figure 10 5 Exiting DPPM Mode Time 4 ms div 20 mA div 100 mA div 2 V div 500 mV div Figure 10 6 Entering B...

Страница 53: ...harger On Off Using CD Time 4 ms div 10 mA div 20 mA div 2 V div 500 mV div Figure 10 9 OVP Fault www ti com BQ25120F3A SLUSDI4A OCTOBER 2018 REVISED APRIL 2021 Copyright 2022 Texas Instruments Incorp...

Страница 54: ...ure 10 12 1 8 VSYS System Efficiency Load Current A Efficiency 1E 6 1E 5 0 0001 0 001 0 01 0 10 2 0 5 40 50 60 70 80 90 100 D010 3 0 V BAT 3 6 V BAT 3 8 V BAT 4 2 V BAT TA 25 C VSYS 2 5 V Figure 10 13...

Страница 55: ...2 V BAT TA 25 C VSYS 2 5 V Figure 10 18 2 5 VSYS Load Regulation Load Current A SYS Output Voltage V 1E 6 1E 5 0 0001 0 001 0 01 0 1 0 5 3 1845 3 2345 3 2845 3 3345 3 3845 D015 3 8 V BAT 4 2 V BAT TA...

Страница 56: ...A 10 PA 100 PA 1 mA 10 mA 100 mA 4 2 TA 25 C VSYS 3 3 V Figure 10 24 3 3 VSYS Line Regulation Load Current mA Frequency F SW kHz 0 50 100 150 200 250 300 0 200 400 600 800 1000 1200 1400 D023 5 V VBAT...

Страница 57: ...Showing SW Time 400 ns div 500 mA div 200 mA div 2 V div 5 V div SW ILOAD 200 mA Figure 10 31 Light Load Operation Showing SW Time 400 ns div 500 mA div 200 mA div 2 V div 5 V div SW ILOAD 300 mA Fig...

Страница 58: ...nt 0 to 50 mA Time 4 s div m 500 mA div 50 mV div 50 mV div 5 V div SW VSYS 3 3 V Figure 10 37 3 3 VSYS Load Transient 0 to 50 mA Time 4 s div m 500 mA div 200 mV div 50 mV div 5 V div SW VSYS 1 2 V F...

Страница 59: ...mA div 200 mV div 50 mV div 5 V div SW VSYS 3 3 V Figure 10 42 3 3 VSYS Load Transient 0 to 200 mA Time 1 ms div 1 V div 5 V div 2 V div Figure 10 43 Startup Showing SS on SYS in PWM Mode Time 20 ms d...

Страница 60: ...nsient 0 to 10 mA Time 4 s div m 50 mV div 5 V div 20 mV div VSLSDO 1 2 V Figure 10 48 1 2 VLSLDO Load Transient 0 to 10 mA Time 4 s div m 50 mV div 5 V div 20 mV div VSLSDO 1 8 V Figure 10 49 1 8 VLS...

Страница 61: ...nt 0 to 100 mA Time 4 s div m 50 mV div 5 V div 100 mV div VSLSDO 1 8 V Figure 10 54 1 8 VLSLDO Load Transient 0 to 100 mA Time 4 s div m 50 mV div 5 V div 100 mV div VSLSDO 2 5 V Figure 10 55 2 5 VLS...

Страница 62: ...Showing SS on LS LDO in LDO Mode Time 20 ms div 200 mA div 2 V div 2 V div Figure 10 58 Short Circuit and Recovery for LDO BQ25120F3A SLUSDI4A OCTOBER 2018 REVISED APRIL 2021 www ti com 62 Submit Doc...

Страница 63: ...Functions as Shifted MR Output Time 400 s div m 500 mV div 2 V div 2 V div 5 V div Figure 10 62 PG Functions as Shifted MR Output Time 200 ms div 2 V div 2 V div 500 mV div 2 V div Wake1 500 ms Wake2...

Страница 64: ...0 67 RESET Timing Time 2 s div 2 V div 2 V div 500 mV div 2 V div Figure 10 68 RESET Timing and Enter Ship Mode 11 Power Supply Recommendations It is recommended to use a power supply that is capable...

Страница 65: ...ce the bypass caps for PMID SYS and LSLDO close to the pins Place the GNDs of the PMID and IN caps close to each other Don t route so the power planes are interrupted 12 2 Layout Example Figure 12 1 B...

Страница 66: ...sign help you need Linked content is provided AS IS by the respective contributors They do not constitute TI specifications and do not necessarily reflect TI s views see TI s Terms of Use 13 5 Electro...

Страница 67: ...1000ppm threshold Antimony trioxide based flame retardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standa...

Страница 68: ...PACKAGE OPTION ADDENDUM www ti com 7 May 2021 Addendum Page 2...

Страница 69: ...SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant BQ25120F3AYFPR DSBGA YFP 25 3000 180 0 8 4 2 65 2 65 0 69 4 0 8 0 Q1 BQ25120F3AYFPT DSBGA YFP 25 250 180 0 8 4 2 65 2...

Страница 70: ...ckage Type Package Drawing Pins SPQ Length mm Width mm Height mm BQ25120F3AYFPR DSBGA YFP 25 3000 182 0 182 0 20 0 BQ25120F3AYFPT DSBGA YFP 25 250 182 0 182 0 20 0 PACKAGE MATERIALS INFORMATION www ti...

Страница 71: ...BALL GRID ARRAY NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis are for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change...

Страница 72: ...nal dimensions may vary due to manufacturing tolerance considerations and also routing constraints See Texas Instruments Literature No SNVA009 www ti com lit snva009 SOLDER MASK DETAILS NOT TO SCALE S...

Страница 73: ...9 2019 DSBGA 0 5 mm max height YFP0025 DIE SIZE BALL GRID ARRAY NOTES continued 4 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release SYMM SYMM SOLDER PAS...

Страница 74: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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