Texas Instruments bq24725, Руководство пользователя

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Bill of Materials, Board Layouts and Schematics
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1. Place input capacitor as close as possible to switching MOSFET ’ s supply and ground connections, and
use shortest copper trace connection. These parts must be placed on the same layer of the PCB
instead of on different layers and vias used to make this connection.
2. The integrated circuit (IC) must be placed close to the switching MOSFET ’ s gate terminals and the
gate drive signal traces kept short for a clean MOSFET drive. The IC can be placed on the other side
of the PCB of switching MOSFETs.
3. Place inductor input terminal to switching MOSFET's output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide
enough to carry the charging current. Do not use multiple layers in parallel for this connection.
Minimize parasitic capacitance from this area to any other trace or plane.
4. The charging current sensing resistor mut be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other
(minimize loop area), and do not route the sense leads through a high-current path. Place decoupling
capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input
capacitor ground before connecting to system ground.
7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the
IC, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
8. Route analog ground separately from power ground. Connect analog ground and power ground
separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or use a 0-
Ω
resistor to tie analog ground to power ground (power pad must tie to
analog ground in this case if possible).
9. Decoupling capacitors must be placed next to the IC pins, and make trace connection as short as
possible.
10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that sufficient thermal vias are directly under the IC, connecting to the ground plane on
the other layers.
4 Bill of Materials, Board Layouts and Schematics
4.1 Bill of Materials
Table 2. Bill of Materials
Count RefDes Value Description Size Part Number MFR
1 C1 2.2 µ F Capacitor, Ceramic, 25V, X7R, 10% 1210 Std Std
6 C2, C3, C4, 10 µ F Capacitor, Ceramic, 25V, X7R, 10% 1206 Std Std
C5, C6, C7
6 C8, C14, C15, 0.1 µ F Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
C16, C17,
C19
4 C9, C10, C20, 1 µ F Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
C25
2 C11, C12 0.01 µ F Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
0 C13, C18, OPEN Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
C24, C26
1 C21 0.047 µ F Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
1 C22 100 pF Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
1 C23 2200 pF Capacitor, Ceramic, 25V, X7R, 10% 603 Std Std
1 D1 BAT54-V-G Diode, Schottky, 200-mA, 30-V SOT23 BAT54-V-G Vishay-Liteon
1 D2 BAT54C-V-G Diode, Dual Schottky, 200-mA, 30-V SOT23 BAT54C-V-G Vishay-Liteon
1 J1 ED120/2DS Terminal Block, 2-pin, 15-A, 5.1mm 0.40 x 0.35 inch ED120/2DS OST
1 J2 ED120/3DS Terminal Block, 3-pin, 15-A, 5.1mm 0.60 x 0.35 inch ED120/3DS OST
2 J3, J4 ED555/3DS Terminal Block, 3-pin, 6-A, 3.5mm 0.41 x 0.25 inch ED555/3DS OST
1 JP1 PEC02SAAN Header, Male 2-pin, 100mil spacing, 0.100 inch x 2 PEC02SAAN Sullins
8 bq24725EVM Evaluation Module SLUU439A – August 2010 – Revised May 2011
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