Printed-Circuit Board Layout Guideline
3. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of
the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and
back to the PGND pin.
4. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do
not place components in such a way that routing interrupts power stage currents). All small control
signals must be routed away from the high-current paths.
5. The printed-circuit board must have a ground plane (return) connected directly to the return of all
components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for
small-signal components). It is also recommended to put vias inside the PGND pads for the IC, if
possible. A star ground design approach is typically used to keep circuit block currents isolated (high-
power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single
ground plane for this design gives good results. This small layout and a single ground plane eliminates
ground-bounce issues, and having the components segregated minimizes coupling between signals.
6. The high-current charge paths into USB, BAT, SYS, and from the SW pins must be sized appropriately
for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins must
be connected to the ground plane to return current through the internal low-side FET.
7. For high-current applications, the balls for the power paths must be connected to as much copper in
the board as possible. This allows better thermal performance because the board conducts heat away
from the IC.
12
QFN-Packaged bq24270/271 Evaluation Modules
SLUU924 – April 2012
Copyright © 2012, Texas Instruments Incorporated
