Printed-Circuit Board Layout Guideline
2.4.2
Helpful Hints
1. The leads and cables to the various power supplies have resistance. The current meters also have
series resistance. Therefore, voltmeters must be used to measure the voltage as close to the IC pins
as possible instead of relying on each supply's digital measurement.
2. When using a sourcemeter that can source and sink current as your battery simulator, it is highly
recommended to add a large (1000 µF+) capacitor at the EVM BAT and GND connectors in order to
prevent oscillations at the BAT pin due to mismatched impedances of the charger output and
sourcemeter input within their respective regulation loop bandwidths. Configuring the sourcemeter for
4-wire sensing eliminates the need for a separate voltmeter to measure the voltage at the BAT pin.
When using 4-wire sensing, always ensure that the sensing leads are connected first in order to
prevent accidental overvoltage by the power leads.
3. For precise measurements of charge current and battery regulation near termination, remove the
current meter in series with the battery or battery simulator. An alternate method for measuring charge
current is to either use an oscilloscope with hall effect current probe or place a 1% or better, thermally
capable (for example, 0.010
Ω
in 1206 or larger footprint) resistor in series between the BAT pin and
battery and measure the voltage across that resistor.
3
Printed-Circuit Board Layout Guideline
Use the following guidelines for PCB layout:
1. To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND,
must be placed as close as possible to the IC.
2. Place 4.7-µF input capacitor as close to PMID pin and PGND pin as possible to make the high-
frequency current loop area as small as possible. Place 1-µF input capacitor GNDs as close to the
respective PMID capacitor GND and PGND pins as possible to minimize the ground difference
between the input and PMID.
3. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of
the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and
back to the PGND pin.
4. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do
not place components such that routing interrupts power stage currents). All small control signals must
be routed away from the high-current paths.
5. The PCB must have a ground plane (return) connected directly to the return of all components through
vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal
components). It is also recommended to put vias inside the PGND pads for the IC, if possible. A star
ground design approach is typically used to keep circuit block currents isolated (high-power/low-power
small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this
design gives good results. With this small layout and a single ground plane, no ground-bounce issue
exists, and having the components segregated minimizes coupling between signals.
6. The high-current charge paths into IN, USB, BAT, SYS, and from the SW pins must be sized
appropriately for the maximum charge current in order to avoid voltage drops in these traces. The
PGND pins must be connected to the ground plane to return current through the internal low-side FET.
7. For high-current applications, the balls for the power paths must be connected to as much copper in
the board as possible. This allows better thermal performance because the board conducts heat away
from the IC.
12
User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A
SLUUAV8A – February 2014 – Revised August 2014
Battery Charger Evaluation Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
