BQ2415x
EVM
DC+
J 1
DC -
BAT+
S
C
L
BAT -
APPLICATION
CIRCUIT
U1
J3
J5
J 4
J2
D1
JMP1
JMP2
JMP3
AUXPWR
CD
S
D
A
D
C
-
D
C
-
S
T
A
T
O
T
G
S
L
R
S
T
JMP5
JMP4
V
I
Power
supply #1
Load
#1
Io
I
I in
USB
Cable
HPA172
Ribbon
Cable
V
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PCB Layout Guideline
2.4.2
Boost Function (For -001, -002, -003, -004, -005, -006, -008 only)
1. Adjust PS#1 output to 3.7V and disable the output. Connect the PS#1 in series with a current meter
(multimeter) to J2 (BAT+, BAT–). Make sure a voltage meter is connected across J2 (BAT+, BAT–).
2. Set the Load #1 current to 200mA ± 20mA but disable the output. Connect the output of the Load #1 in
series with a current meter (multimeter) to J1 (DC+, DC–). Make sure a voltage meter is connected
across J1 (DC+, DC–). The setup is now like
for HPA256.
Figure 5. Test setup for HPA256
3. Turn on PS#1 output
4. Software setup: Change Operation Mode to Boost Mode.
Measure
→
V(J1(DC+, DC–))=5V ± 0.2V
5. Enable Load #1.
Measure
→
V(J1(DC+, DC–))=5V ± 0.2V
Measure
→
Iin = 330mA ± 40mA
Measure
→
Io = 200mA ± 20mA
3
PCB Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from input to PGND, should be
placed as close as possible to the IC.
2. The output inductor should be placed close to the IC and the output capacitor connected between the
inductor and PGND of the IC. The intent is to minimize the current path loop area from the SW pin
through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper
layout to minimize high frequency current path loop is critical.
3. The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the
sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or
on top of each other on adjacent layers (do not route the sense leads through a high-current path).
4. Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be
routed away from the high current paths.
5. The PCB should have a ground plane (return) connected directly to the return of all components
through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per
capacitor for small-signal components). A star ground design approach is typically used to keep circuit
block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and
ground-bounce issues. A single ground plane for this design gives good results. With this small layout
and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
6. The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
7
SLUU321B – June 2008 – Revised May 2010
bq2415x YFF EVM
Copyright © 2008–2010, Texas Instruments Incorporated