Texas Instruments AN-1662 LMV551, Руководство пользователя

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R
F
R
G
Inverting gain:
Layout Considerations
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For inverting gain operation, the gain is set by Equation 2 :
Select R
T
to yield the desired input impedance (input impedance = R
G
||R
T
). (2)
To minimize offset voltages, R
IN
should equal the parallel combination of R
G
and R
T
with R
F
as shown in
Equation 3 :
R
IN
= (R
G
+ R
T
)||R
F
(3)
The output of the op amp travels through a series resistance, Rout, and then leaves the board through an
SMA connector. The series resistance, R
OUT
, matches transmission lines and isolates the output from
capacitive loads.
3 Layout Considerations
General layout and supply bypassing play major roles in high frequency performance. When designing
your own board, use the evaluation board as a guide and follow these steps as a basis for high frequency
layout:
1. Use a ground plane.
2. Include 6.8 μ F tantalum (C1, C2), and 0.1 μ F ceramic (C3, C6) capacitors, on both supplies.
3. Place the 6.8 μ F capacitors within 0.75 inches of the power pins.
4. Place the 0.1 μ F capacitors less than 0.1 inches from the power pins.
5. Place 0.01 μ F ceramic capacitors (C4, C5) as optional decoupling.
6. Remove the ground plane under and around the part, especially near the input and output pins to
reduce parasitic capacitance.
7. Minimize all trace lengths to reduce series inductances.
4 Evaluation Board
Figure 2. Layer 1
2 AN-1662 LMV551 Evaluation Board SNOA492A – July 2007 – Revised April 2013
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