Ethernet Ports
19
SPRUI64E – May 2017 – Revised September 2019
Copyright © 2017–2019, Texas Instruments Incorporated
AM572x Industrial Development Kit (IDK) Evaluation Module (EVM)
Hardware
6
Ethernet Ports
The AM572x IDK EVM supports up to four 100Mb Industrial Ethernet ports attached to the PRU-ICSS
subsystems and up to two Gigabit (1000Mb) Ethernet ports connected to the integrated Ethernet switch.
The final number of available ports depends on the configuration options. The default configuration
provides two 100Mb Industrial Ethernet ports and two Gigabit (1000Mb) Ethernet ports.
6.1
100Mb Ethernet Ports on PRU-ICSS
The AM572x IDK EVM contains four 100Mb Ethernet ports that each connect to an industrial
PHY/Transceiver (TLK105L), which then connect to RJ45 metallic connectors, with integrated magnetics,
J3, J5, J6, and J8. These Ethernet transceivers are connected to the PRU1 and PRU2 subsystems within
the AM5728 processor.
shows the mapping from the PRU-ICSS ports to the RJ45 connectors.
The COL functionality on the MII interface is not used. The TLK105L contains a feature that must be
enabled via software that provides rapid link status on the COL pin. Therefore, this pin is connected to the
RXLINK input to the PRU-ICSS ports for this purpose.
Test headers J4 and J7 are available to support real-time code development. The signals contained are
available for simplified probing.
The reset for the transceivers is driven low coincident with the PORz reset to the AM5728 processor. The
reset for each transceiver can also be driven low individually by separate GPIO signals from the
processor. A 25-MHz clock is provided into each of the TLK105L industrial transceivers.
Table 4. PRU-ICSS Ethernet Ports
Connector
PRU-ICSS Port
MDIO Address
Notes
J3
PRU1ETH0
0x0 on PRU1
Not available in default configuration. MII pins multiplexed with RGMII0.
J5
PRU1ETH1
0x1 on PRU1
Not available in default configuration. MII pins multiplexed with RGMII1.
J6
PRU2ETH0
0x0 on PRU2
J8
PRU2ETH1
0x1 on PRU2
6.2
Gigabit (1000Mb) Ethernet Ports
The AM572x IDK EVM contains two Gigabit (1000Mb) Ethernet PHY/Transceivers (KSZ9031RN)
interfaced to connectors J10 (RGMII0) and J12 (RGMII1). These Gigabit Ethernet transceivers are
connected over RGMII0 and RGMII1 to the Ethernet switch block within the AM5728 processor.
The resets for the transceivers are driven low coincident with the PORz reset to the AM5728 processor. A
25-MHz clock is provided into each of the KSZ9031RN Gigabit transceivers.
