Functional Description
12
SPRUI64E – May 2017 – Revised September 2019
Copyright © 2017–2019, Texas Instruments Incorporated
AM572x Industrial Development Kit (IDK) Evaluation Module (EVM)
Hardware
2.1
Processor
The AM5728 processor is the central processing unit for this IDK EVM. The interface circuitry, memory
ICs, and connectors implemented on the board around the AM5728 processor provide development
support for the many industrial communication interfaces available on this platform. See the
Sitara Processors Silicon Revision 2.0 Data Manual (SPRS982)
and the
Technical Reference Manual (SPRUHZ6)
for details about the processor.
The AM572x IDK EVM contains system configuration for the boot mode control inputs SYSBOOT[15..0].
These can be strapped using resistors. The default configuration will meet the needs of most developers.
Resistor reconfiguration is supported so that you can explore other boot configurations of the AM572x
processor. See
for more details.
2.2
Clocks
The main clock for the processor is derived from a 20-MHz crystal. An on-board oscillator in the AM572x
processor generates the base clock and the subsequent module clocks as needed within the AM572x
processor. The board design supports a crystal attached to the RTC block, but this is not needed since
RTC-only mode is not supported in this device.
2.3
Reset Signals
The AM572x processor contains 3 reset inputs and an output indicating a reset is in progress. The reset
pins are:
•
PORz: PORz is a hard reset that resets everything including emulation logic. It also tri-states most
outputs.
•
RESETn: RESETn is a device reset commonly driven by control logic or emulation.
•
RTC_PORz: Separate PORz for the RTC module that must be driven at the same time as PORz.
(Note that PORz and RTC_PORz can only be directly connected as long as VDDSHV3 and VDDSHV5
are driven at the same voltage.)
•
RSTOUTn: Output signal from SOC indicating that the device has entered reset. This is used to reset
other circuits that must be reset at the same time as the processor.
More details about the behavior of these reset pins within the AM572x processor can be found in the
AM572x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS982)
. There are push buttons on the
IDK that can initiate either a RESETn or PORz input. SW1 can drive PORz active (low) and SW2 can
drive RESETn active (low).
There is a device erratum in all of the AM572x devices that prevents use of RESETn independent from
PORz. The workaround is to generate PORz whenever a device reset occurs even if it is from an internal
initiator. This is accomplished through cooperation with the PMIC paired with the AM572x device on the
IDK EVM. The RSTOUTn output from the AM572x device is connected to the NRESWARM input of the
PMIC. This initiates a re-start that drives RESET_OUT low and resets all voltages to their initial values.
Since RESET_OUT from the PMIC is connected to PORz in the AM572x device, a hard reset is forced on
the SOC that meets the needs of the erratum workaround.
The AM572x IDK EVM is started by pressing the start-up push button, SW3. The POWERHOLD input can
be connected to VRTC_OUT in customer designs to cause the board to power-on as soon as the main
supply is stable.
The configuration of the PMIC to provide RESET_OUT from the NRESWARM input creates an always-on
implementation. This always-on mode of operation prevents software shut-down of the IDK. Customer
designs should have power-good monitoring circuitry such as a TPS3808 connected to the main supply to
the PMIC that is connected to the PMIC RESET_IN. The TPS3808 can detect the main supply voltage
dropping and then trigger the PMIC to execute a controlled shut-down that meets the requirements in the
AM572x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS982)
.
