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PCB Guideline Deviations
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14 SPRUII2 – November 2017
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AM437x IDK Evaluation Hardware
6 PCB Guideline Deviations
Table 16 lists the PCB guidelines deviation, with respect to the data sheet.
Table 16. PCB Guidelines Deviations
Serial.No. PCB Design Guidelines Data Sheet
Reference Deviation Reason For Deviation
1 Full VDDS_DDR power reference
layers under the DDR3 routing
region Table 5-35 Signals other than DDR
in layer 4 are also
referenced with the
VDDS_DDR power
plane. Due to space constraints
2 Placement X2 (DDR device 1 to
DDR device 2 distance) – 600 mils
(maximum) Table 5-36 740 mils To enable ease of routing
3 VDDS_DDR bulk bypass capacitor,
2-count devices (minimum) Table 5-37 Only one bulk capacitor
used Due to space constraints
4 VDDS_DDR bulk bypass total
capacitance 20
μ
F (minimum)
Table 5-37 Two, 10 µF capacitors
required, but only one 10
µF capacitor used Due to space constraints
5 DDR3 bulk bypass capacitor, 2-count
devices (minimum) Table 5-37 One device (22 µF)
capacitor used Due to space constraints
6 DDR3 bulk bypass total capacitance
20
μ
F (minimum)
Table 5-37 One, 22 µF capacitor
used Due to space constraints
7 VDDS_DDR HS bypass capacitor,
20-count devices (minimum) Table 5-38 Six bypass capacitors
used Due to space constraints
8 VDDS_DDR HS bypass capacitor
total capacitance 1
μ F ( minimum)
Table 5-38 Six, 0.01 µF capacitors
used Due to space constraints
9 DDR device 1 to DDR device 2:
DDR3 device HS bypass capacitor
total capacitance – 0.85
μ F
(minimum)
Table 5-38 14, 0.01 µF capacitors
used Due to space constraints
10 CK and ADDR_CTRL nominal trace
length – 100 mils (maximum) Table 5-41 More than 200 mils
difference Due to space and routing
constraints
11 Split plane crossing 5.6.2.1.3.3 Found across the board Due to space and routing
constraints