108-032
spim_csx
spim_simo
spim_clk
Transmitter buffer
Shift register
Master
Control
Receiver register
(single)
Control
Shift register
Master SPI shift register
Initial
After 8 spim_clk
clock cycles
WordA
WordC
Slave SPI shift register
Initial
WordB
WordA
After 8 spim_clk
clock cycles
Receiver register
Slave
(receive only)
Functional Description
Transmitter register or FIFO (if enabled) content is always loaded into the shift register whether it has
been updated or not. The event TX_underflow is activated accordingly, and does not prevent
transmission.
On completion of SPI word transfer (bit EOT of the register MCSPI_CH(I)STAT is set) the received data is
transferred to the channel receive register. This bit is meaningless when using the Buffer for this channel.
The built-in FIFO is available in this mode and can be configured in one data direction, transmit or receive,
then the FIFO is seen as a unique 64-byte buffer. It can also be configured in both data directions,
transmit and receive, then the FIFO is split into two separate 32-byte buffers with their own address space
management.
24.3.3.4 Slave Receive-Only Mode
The slave receive mode is programmable (MCSPI_CH(i)CONF[TRM set to 01).
In receive-only mode, the transmitter register should be loaded before McSPI is selected by an external
SPI master device. Transmitter register or FIFO (if enabled) content is always loaded into the shift register
whether it has been updated or not. The event TX_underflow is activated accordingly, and does not
prevent transmission.
When an SPI word transfer completes (the MCSPI_CH(I)STAT[EOT] bit (with I = 0) is set to 1), the
received data is transferred to the channel receive register.
To use McSPI as a slave receive-only device with MCSPI_CH(I)CONF[TRM]=00, the user has the
responsibility to disable the TX_empty and TX_underflow interrupts and DMA write requests due to the
transmitter register state.
On completion of SPI word transfer (bit EOT of the register MCSPI_CH(I)STAT is set) the received data is
transferred to the channel receive register. This bit is meaningless when using the Buffer for this channel.
The built-in FIFO is available in this mode and can be configured with FFER bit field in the
MCSPI_CH(I)CONF register, then the FIFO is seen as a unique 64-byte buffer.
shows an example of a half-duplex system with a master device on the left and a receive-
only slave device on the right. Each time one bit transfers out from the master, one bit transfers in to the
slave. If WordA is 8 bits, then after eight cycles of the serial clock spim_clk, WordA transfers from the
master to the slave.
Figure 24-24. SPI Half-Duplex Transmission (Receive-Only Slave)
4025
SPRUH73H – October 2011 – Revised April 2013
Multichannel Serial Port Interface (McSPI)
Copyright © 2011–2013, Texas Instruments Incorporated