1129
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Multichannel Audio Serial Port (McASP)
24.0.21.6.5 DMA Error - Receiver
A receive DMA error, as indicated by the RDMAERR flag in the RSTAT register, occurs when the DMA (or
CPU) reads more words from the DMA port of the McASP than it should. For each DMA event, the DMA
should read exactly as many words as there are serializers enabled as receivers.
RDMAERR indicates that the DMA (or CPU) read too many words from the McASP for a given receive
DMA event. Reading too few words results in a receiver overrun error setting ROVRN in RSTAT.
While RDMAERR occurs infrequently, an occurrence indicates a serious loss of synchronization between
the McASP and the DMA or CPU. You should reinitialize both the McASP receiver and the DMA to
resynchronize them.
24.0.21.6.6 Clock Failure Detection
24.0.21.6.6.1
Clock-Failure Check Startup
It is expected, initially, that the clock-failure circuits will generate an error until at least one measurement
has been taken. Therefore, the clock failure interrupts, clock switch, and mute functions should not
immediately be enabled, but be enabled only after a specific startup procedure. The startup procedure is:
1. For the transmit clock failure check:
(a) Configure transmit clock failure detect logic (XMIN, XMAX, XPS) in the transmit clock check control
register (XCLKCHK).
(b) Clear transmit clock failure flag (XCKFAIL) in the transmit status register (XSTAT).
(c) Wait until first measurement is taken (> 32 AHCLKX clock periods).
(d) Verify no clock failure is detected.
(e) Repeat steps b–d until clock is running and is no longer issuing clock failure errors.
(f) After the transmit clock is measured and falls within the acceptable range, the following may be
enabled:
(i) transmit clock failure interrupt enable bit (XCKFAIL) in the transmitter interrupt control register
(XINTCTL)
(ii) transmit clock failure detect autoswitch enable bit (XCKFAILSW) in the transmit clock check
control register (XCLKCHK)
(iii) mute option (XCKFAIL) in the mute control register (AMUTE)
2. For the receive clock failure check:
(a) Configure receive clock failure detect logic (RMIN, RMAX, RPS) in the receive clock check control
register (RCLKCHK).
(b) Clear receive clock failure flag (RCKFAIL) in the receive status register (RSTAT).
(c) Wait until first measurement is taken (> 32 AHCLKR clock periods).
(d) Verify no clock failure is detected.
(e) Repeat steps b–d until clock is running and is no longer issuing clock failure errors.
(f) After the receive clock is measured and falls within the acceptable range, the following may be
enabled:
(i) receive clock failure interrupt enable bit (RCKFAIL) in the receiver interrupt control register
(RINTCTL)
(ii) mute option (RCKFAIL) in the mute control register (AMUTE)