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PLLC Registers
7.3.5 PLLC0 Control Register (PLLCTL)
The PLLC0 control register (PLLCTL) is shown in
and described in
.
Figure 7-6. PLLC0 Control Register (PLLCTL)
31
16
Reserved
R-0
15
10
9
8
Reserved
EXTCLKSRC
CLKMODE
R-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
Reserved
PLLENSRC
Reserved
PLLRST
Reserved
PLLPWRDN
PLLEN
R-1
R/W-1
R/W-1
R/W-0
R-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-8. PLLC0 Control Register (PLLCTL) Field Descriptions
Bit
Field
Value
Description
31-10
Reserved
0
Reserved
9
EXTCLKSRC
External clock source selection.
0
Use OSCIN for the PLL bypass clock.
1
Use PLL1_SYSCLK3 for the PLL bypass clock.
8
CLKMODE
Reference clock selection.
0
Internal oscillator (crystal)
1
Square wave
7-6
Reserved
1
Reserved
5
PLLENSRC
0
This bit must be cleared before the PLLEN bit will have any effect.
4
Reserved
1
Reserved. Write the default value when modifying this register.
3
PLLRST
PLL0 reset.
0
PLL0 reset is asserted.
1
PLL0 reset is not asserted.
2
Reserved
0
Reserved
1
PLLPWRDN
PLL0 power-down.
0
PLL0 is operating.
1
PLL0 is powered-down.
0
PLLEN
PLL0 mode enables.
0
PLL0 is in bypass mode.
1
PLL0 mode is enabled, not bypassed.
81
SPRUGX5A
–
May 2011
Phase-Locked Loop Controller (PLLC)
Copyright
©
2011, Texas Instruments Incorporated
Содержание AM1802
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