1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
Revision History
Date
Notes
Initial Release
A
SIZE
SCHEMATIC,
B
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this
specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for
any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate
and test your design implementation to confirm the system functionality for your application.
EVM,
6573934
http://www.ti.com
© Texas Instruments 2014
ADS8688
DRAFTSMAN:
DESIGNER:
CHECKER:
ENGINEER:
APPROVED:
RELEASED:
DATE:
DATE:
DATE:
DATE:
DATE:
DATE:
B McKay
B McKay
Lokesh Ghulyani
Lokesh Ghulyani
B McKay
B McKay
3/13/2014
3/13/2014
3/13/2014
3/13/2014
3/13/2014
3/13/2014
TITLE:
SCALE
N
REV
C
SHEET
1
1
T
I
FID5
FID4
FID6
DVDD
RST/PD
47.0k
R13
47.0k
R15
DAISY
GND
RST/PD
DAISY
10µF
C5
GND
GND
1µF
C9
22µF
C8
GND
AVDD
GND
REFOUT
AVDD
AUX+
GND
47.0k
R18
REFSEL
REFSEL
0.1µF
C2
DVDD
GND
100
R19
0.1µF
C6
GND
R
E
F
O
U
T
REFIN
0.1µF
C3
GND
REFIN
CS
SCLK
SDI
ANALOG INPUTS
357
R23
357
R25
357
R27
357
R29
357
R31
357
R34
357
R37
357
R40
357
R41
357
R38
357
R35
357
R32
357
R30
357
R28
357
R26
357
R24
1
2
3
J10
10µF
C7
TP11
09/16/2013
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
16
18
20
A107012CT-ND
J1
TSM-110-01-T-DV-P
GND
S
C
L
K
C
S
R
S
T
/P
D
D
A
IS
Y
R
E
F
S
E
L
0
R4
S
D
I
S
D
O
A
3V3_LP
VBUS_LP
PRJ_Number
PCB_Rev
PCB Number:
PCB Rev:
0.01uF
C12
0.01uF
C13
0.01uF
C14
0.01uF
C15
0.01uF
C19
0.01uF
C18
0.01uF
C20
0.01uF
C21
49.9
R6
49.9
R7
49.9
R9
49.9
R8
49.9
R3
49.9
R2
49.9
R5
49.9
R16
1
2
3
J11
TSW-103-07-G-S
1
2
3
J9
TSW-103-07-G-S
1
2
3
J8
SDO
TP10
RefOut
TP6
TP7
TP8
TP9
TP2
TP3
TP4
TP5
A6-
A7-
A0-
A1-
1µF
C10
GND
GND
A2-
A3-
A4-
A5-
J1-3
J1-5
J1-7
J1-9
J1-11
J1-14
J1-16
J1-18
J1-20
AUX-
FID2
FID1
FID3
GND
1µF
C63
AVDD
SDI
1
RSTZ/PDZ
2
DAISY
3
REFSELZ
4
REFIO
5
REFGND
6
REFCAP
7
AGND
8
AVDD
9
AUX_IN
10
AUX_GND
11
AIN_6P
12
AIN_6GND
13
AIN_7P
14
AIN_7GND
15
AIN_0P
16
AIN_0GND
17
AIN_1P
18
AIN_1GND
19
AIN2_GND
20
AIN_2P
21
AIN_3GND
22
AIN_3P
23
AIN_4GND
24
AIN_4P
25
AIN_5GND
26
AIN_5P
27
AGND
28
AGND
29
AVDD
30
AGND
31
AGND
32
DGND
33
DVDD
34
NC
35
SDO
36
SCLK
37
CS~
38
ADS8688DBT
U2
ADS8688DBT
10.0k
R1
AVDD
GND
0.1µF
C1
GND
49.9
R10
AUX+
GND
A0+
A1+
A6+
A7+
A5+
A4+
A3+
A2+
10.0Meg
R11
NT1
Net-Tie
GND
AUX-
This allows the connection of two nets,
without compiler errors or a physical component.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
16
18
20
A107012CT-ND
J7
TSM-110-01-T-DV-P
A0-
A0+
A1+
A1-
A2-
A2+
A3-
A3+
49.9
R14
1
2
J16
1
2
J22
1
2
J23
1
2
J24
1
2
J26
1
2
J27
1
2
J28
1
2
J29
1
2
J25
1
2
J15
1
2
J30
1
2
J31
4
3
2
1
5
V+
V-
U1
OPA320AIDBVR
GND
B
12/09/2013
Added RefOut, Aux Buffer Ckts
1
2
J21
1
2
J2
1
2
J3
1
2
J4
1
2
J5
1
2
J6
A6-
A7-
A7+
A6+
A4-
A4+
A5-
A5+
A1+
A0+
3
2
1
4
8
V+
V-
U4A
OPA2209AIDGKR
GND
HVDD
GND
HVSS
0
R33
GND
GND
6.65k
R43
3.57k
R42
2200pF
C17
1000pF
C23
1
0
.0
M
e
g
R22
0.1µF
C16
0.1µF
C24
5
6
7
U4B
OPA2209AIDGKR
0
R39
2200pF
C22
GND
6.65k
R45
GND
1
0
0
0
p
F
C25
1
0
.0
M
e
g
R76
3.57k
R46
A2+
A3+
0
R49
2200pF
C28
6.65k
R53
3.57k
R54
GND
GND
1000pF
C31
5
6
7
U5B
OPA2209AIDGKR
1
0
.0
M
e
g
R21
HVDD
HVSS
GND
GND
GND
0
R47
GND
2200pF
C27
6.65k
R51
3.57k
R50
1
0
0
0
p
F
C29
3
2
1
4
8
V+
V-
U5A
OPA2209AIDGKR
1
0
.0
M
e
g
R74
0.1µF
C30
0.1µF
C26
Bumpers to be placed on backside of board
H1
SJ5202
H2
SJ5202
H3
SJ5202
H4
SJ5202
0.01uF
C4
NI
R36
NI
R44
NI
R52
NI
R48
SH-J2
SH-J3
SH-J4
SH-J5
SH-J6
SH-J8
SH-J9
SH-J10
SH-J11
SH-J12
SH-J13
SH-J14
SH-J15
SH-J16
SH-J17
SH-J21
SH-J22
SH-J23
SH-J24
SH-J25
SH-J26
SH-J27
SH-J28
SH-J29
SH-J30
SH-J31
This design uses SanDisk Micro SD Card, 2GB, p/n SDSDQ-002G
3000pF
C11
4
3
2
1
5
V+
V-
U3
OPA320AIDBVR
Added SD Card, minor value changes
03/13/2014
C