Texas Instruments ADS8568EVM-PDK, Руководство пользователя, Страница: 5 / 35

2 EVM Analog Interface
2.1 ADC Supply, Input, Voltage Reference, and Digital Connections
Figure 2-1 illustrates the decoupling on AVDD, DVDD, HVDD, HVSS, and the reference IO. The capacitors
for decoupling match the recommendations in the ADS8568 data sheet. The layout (see Figure 2-1 ) uses the
shortest possible connections to the decoupling capacitors and connections the ground end to the GND plane
using vias. The ADS8568 can use an external or internal voltage reference. This can be selected by changing
the position of JP9 to “INT” for internal, or “EXT” for external.
Figure 2-1 also illustrates the analog input signal
and digital signal connections.
A0
A1
B0
B1
C0
C1
D0
D1
GND
AVDD
GND
DB0_DCIND
DB1_DCINC
DB2_DCINB
DB3_DCINA
DB4
DB5_SELCD
DB6_SELB
DB7
DB8_DCEN
DB9_SDI
DB10_SCLK
DB11_REFBUFEN
DB12_SDOA
DB13_SDOB
DB14_SDOC
DB15_SDOD
GND
GND
GND
GND
BUSY
RANGE_XCLK
~HW_SW
REFEN_~WR
~STBY
~CS_~FS
~RD
ASLEEP
~PAR_SER
CONVSTA
CONVSTB
CONVSTC
CONVSTD
DVDD
HVDD
HVSS
HVSS
1
CH_D1
2
REFDN
3
AVDD
4
AGND
5
REFDP
6
CH_D0
7
PAR/SER
8
STBY
9
RESET
10
REFEN/WR
11
RD
12
CS/FS
13
AVDD
14
AGND
15
DB15/SDO_D
16
DB14/SDO_C
17
DB13/SDO_B
18
DB12/SDO_A
19
DB11/REFBUFEN
20
DB10/SCLK
21
DB9/SDI
22
DB8/DCEN
23
DGND
24
DVDD
25
DB7
26
DB6/SEL_B
27
DB5/SEL_CD
28
DB4
29
DB3/DCIN_A
30
DB2/DCIN_B
31
DB1/DCIN_C
32
DB0/DCIN_D
33
RANGE/XCLK
34
BUSY/INT
35
ASLEEP
36
CONVST_A
37
CONVST_B
38
CONVST_C
39
CONVST_D
40
HW/SW
41
CH_A0
42
REFAP
43
AGND
44
AVDD
45
REFBN
53
CH_A1
47
HVDD
48
CH_B0
49
REFBP
50
AGND
51
AVDD
52
REFAN
46
CH_B1
54
REFN
55
REFIO
56
AVDD
57
AGND
58
CH_C1
59
REFCN
60
AVDD
61
AGND
62
REFCP
63
CH_C0
64
ADS8568SPM
U5
GND GND
GND GND
GND
GND
VIN
1
SS
3
FILT
4
EN
2
OUT_S
5
OUT_F
6
GND_F
7
GND_S
8
REF6025IDGKR
U6
AVDD
GND
GND
GND
GND
120k
R108
GND
10uF
C43
10uF C45
10uF C46
10uF C47
10uF C48
10uF
C53
10uF
C54
0.47uF
C49
22uF
C55
0.22
R109
RET_RD
RET_SCLK
10uF
C51
49.9 R71
49.9 R70
49.9 R73
49.9 R74
49.9 R75
49.9 R79
49.9 R76
49.9 R80
49.9 R81
49.9 R82
49.9 R83
49.9 R84
49.9 R85
49.9 R87
49.9
R88
49.9 R89
49.9 R65
49.9 R92
49.9 R93
49.9 R94
49.9 R96
49.9 R68
49.9 R66
49.9 R67
49.9
R95
49.9 R97
49.9 R98
49.9 R100
49.9 R99
49.9 R101
~CS_~FS
~RD
ASLEEP
~PAR_SER
RANGE_XCLK
~HW_SW
REFEN_~WR
~STBY
RESET
100nF
C37
100nF
C38
100nF
C39
100nF
C40
100nF
C41
100nF
50V
C42
100nF
50V
C44
100nF
C50
100nF
C52
0 R69
0 R86
0 R107
1
2 3
JP9
TP4
Vref
RESET
1.00
R104
1.00
R72
EXT INT
Figure 2-1. ADC Signal and Supply Connection
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SBAU193E – JUNE 2011 – REVISED MAY 2021
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ADS8568EVM-PDK Evaluation Module 5
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