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As described in Table 1-7 , this evaluation module provides direct access all the analog-to-digital converter
control signals via connector J3.
Table 1-7. Pin Out for Converter Control Connector J3
Connector.Pin
(1)
Signal Description
J3.1 CS Chip-select pin. Active low.
J3.3 RD Read pin. Active low.
J3.5 CONVST Convert start pin. Active low.
J3.7 BYTE BYTE mode pin. Used for 8-bit buses.
J3.9 PWD/RST Active low input, acts as device power down or device reset signal.
J3.11 A_PDWN Nap mode enable, active low.
J3.13 BUSY Converter status output. High when a conversion is in progress.
(1) All even-numbered pins of J3 are tied to DGND.
1.4 Power Supplies
The EVM accepts four power supplies.
• A dual ±Vs DC supply for the dual-supply op amps. A ±12-V DC supply is recommended.
• A 5.0-V DC supply for the analog section of the board (ADC + reference).
• A 5.0-V or +3.3-V DC supply for the digital section of the board (ADC + address d buffers).
There are two ways to provide these voltages.
1. Wire in voltages, as listed in Table 1-8 , at test points on the EVM.
Table 1-8. Power-Supply Test Points
Test Point Signal Description
TP11 +BVDD Apply a +3.3-V DC or +5.0-V DC voltage. See the respective ADC data sheet for the full range.
TP10 +AVCC Apply a +5.0-V DC voltage.
TP12 +VA Apply a +12.0-V DC voltage. Positive supply for the amplifier.
TP14 –VA Apply a –12.0-V DC voltage. Negative supply for the amplifier.
1. Use the power connector J1 and derive the voltages elsewhere. Table 1-9 lists the pin out connections for
J1. Set jumper W5 to short between pins 1-2 or pins 2-3 to short +3.3VD or +5VD, respectively, to be the
buffer digital supply (+BVDD).
Table 1-9. Power Connector, J1, Pin Out
Signal Power Connector - J1 Signal
+VA (+12VA) 1 2 –VA (–12VA)
+AVCC (+5VA) 3 4 N/C
N/C 5 6 AGND
N/C 7 8 N/C
+3.3VD 9 10 +5VD
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6 ADS7881EVM, ADS7891EVM Evaluation Module SLAU150A – DECEMBER 2004 – REVISED OCTOBER 2021
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