Texas Instruments ADS7853EVM-PDK, Руководство пользователя, Страница: 11 / 41

www.ti.com
ADSxx53EVM-PDK Initial Setup
5 ADSxx53EVM-PDK Initial Setup
This section presents the steps required to set up the ADSxx53EVM-PDK kit before operation.
5.1 Default Jumper Settings
Figure 6 shows the silkscreen plot detailing the default jumper settings. Table 6 descibes the configuration
for these jumpers.
Figure 6. ADSxx53EVM Default Jumper Settings
Table 6. Default Jumper Configuration
Pin Number Default Position Switch Description
JP1 Open JP1.2 Header connector to inverted AINP-A input
JP2 Open JP2.2 Header connector to inverted AINP-B input
JP3 Closed Closed when configured in 0 to 1 × V
ref
range; open to support 0 to 2 × V
ref
range
JP4 Closed Closed when configured in 0 to 1 × V
ref
range; open to support 0 to 2 × V
ref
range
Closed to connect onboard 2.5-V reference to REFIO_A; open when using ADSxx53
JP5 Closed
internal reference.
Closed to connect onboard 2.5-V reference to REFIO_B; open when using ADSxx53
JP6 Closed
internal reference.
JP7 Shunt 1-2 Shunt 1-2 connects AINM-A(–) to GND; shunt 2-3 connects AINM-A(–) to FSR / 2.
JP8 Shunt 1-2 Shunt 1-2 connects AINM-B(–) to GND; shunt 2-3 connects AINM-B(–) to FSR / 2 .
JP9 Closed Open for channel A unipolar input signals at SMA connector; installed for channel A
bipolar input signals at SMA connector
JP10 Closed Open for channel B unipolar input signals at SMA connector; installed for channel B
bipolar input signals at SMA connector
JP11 Open Open: onboard AVDD set to +5 V; closed: onboard AVDD set to +5.2 V
Shunt 2-3 selects onboard regulated AVDD supply; shunt 1-2 selects external AVDD
JP12 Shunt 2-3
through J5
11 SBAU210A – June 2014 – Revised August 2014 ADS8353EVM-PDK and ADS7853EVM-PDK
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated