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GND
6 V
J2
J3
TPS62420
JP2
1
TPS7A8001
LDO 3.3 V
To ADC
To ADC
PWR IN
J1
TPS2400
JP3
1
JP6
1
TPS7A8001
LDO 1.9 V
JP5
1
Overvoltage
Protection Circuit
Dual Output
DC/DC Converter
Low Noise LDO
Low Noise LDO
Introduction
3
SLAU455B – August 2012 – Revised May 2016
Copyright © 2012–2016, Texas Instruments Incorporated
ADS58H4x (ADS58H40/ADS58H43) EVM
The clock input is supplied by way of a single-ended signal to an SMA connector and transformer coupled
producing a differential clock signal for the ADS58H4x.
Power to the EVM is typically supplied by a single 6-V power brick. Banana jacks may also be used to
supply power to the EVM. All necessary voltages for the ADS58H4x are derived from the 6-V input
connection.
1.2
EVM Power Supply
illustrates the power supply options available on the EVM. Jumpers are used to choose the
power supply options, with the default jumper positions indicated by the darker portion of the jumper that
represents the presence of the jumper. For jumper and feedback resistor configuration, see
.
Figure 2. Simplified ADS58H4x EVM Power Supply
Table 1. Power Supply Options
Power Supply
Options
JP2
JP3
JP4
JP5
R3
R7
Comment
Option #1
(Default)
1-2
1-2
1-2
1-2
649
k
Ω
536
k
Ω
Dual outputs DC/DC converter supplies 3.85 V and 2.4 V to two
low-noise LDOs. The low-noise LDOs output 3.3 V and 1.9 V,
respectively.
Option #2
2-3
2-3
2-3
2-3
536
k
Ω
390
k
Ω
Low-noise LDOs are bypassed. DC/DC converter powers the
ADC directly.
The default power path has an efficient dual output DC-DC switching power supply to first step down the
input supplies for the low-noise LDOs. The low-noise LDOs generate the 3.3 V and 1.9 V for the ADC
power.
The low-noise LDOs can be bypassed, allowing the DC/DC power supply to directly power the ADC. In
this implementation, adjust the feedback resistors of the DC/DC converter accordingly.