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Alternate Hardware Configurations
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14 SLAU687 – May 2016
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ADS54J20EVM
5 Alternate Hardware Configurations
This section describes alternate hardware configurations in order to achieve better results or to more
closely mimic the system configuration.
5.1 Clocking Options
The default clocking mode uses the LMK04828 to generate the ADC sampling clock and FPGA clocks.
There are three additional clocking options that the EVM supports. These options are described in the
following sections.
5.1.1 External ADC Sampling Clock
An external clock can be used as the sampling clock for the ADC. This clock can be provided through a
transformer using the
EXT_ADC_CLK connector (J5). For this option, C65 and C73 need to be uninstalled
and installed at C64 and C72. The LMK04828 must still be used to provide the device clock to the
TSW14J56 and the SYSREF signals to both boards. This option provides the best performance, as long
as the clock source has better phase-noise performance than the LMK04828. The source of the EXT ADC
clock must be synchronized with the LMK04828. To accomplish this, send the 10-MHz reference output
from the signal generator and connect it to J6 (CLKIN) of the ADS54J20EVM. This causes LED D1 to
illuminate indicating the LMK VCXO source is locked to the external reference clock. The provided LMK
configuration files will work in this mode as well. If D1 does not illuminate, the signal from the outside
source may be to low. To correct for this, click on the LMK04828 tab at the top of the GUI. When the
LMK04828 page opens, click on the "PLL1 Configuration" tab. On the left middle side of the GUI, change
the Buffer Type of CLKin1 from "Bipolar" to "CMOS" as shown in
Figure 8 .
Figure 8. GUI CMOS Selection