Texas Instruments ADS1282EVM, Руководство пользователя, Страница: 4 / 38

Digital Interface
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The input pins on the ADS1282EVM are directly connected to the part, with no filtering or protection. It is
important that appropriate caution is taken when handling the pins.
Table 1 summarizes the pinouts for
analog interface J6.
Table 1. J6: Analog Interface Pinout
Pin Number Signal Description
J6.1 A1N AINN1, ADS1282
J6.2 A1P AINP1, ADS1282
J6.3 A2N AINN2, ADS1282
J6.4 A2P AINP2, ADS1282
J6.9-13 (odd) AGND Analog ground connections
J6.15 VCOM
J6.17-19 (odd AGND Analog ground connections
J6.18 REFN External reference source input ( –
side of differential input)
J6.20 REFP External reference source input (+
side of differential input)
J6.5-8 Unused
J6.10-16 (even) Unused
3 Digital Interface
3.1 Serial Data Interface
The ADS1282EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J5. This header/socket provides access to the digital control and serial data pins of the
ADC. Consult Samtec at
http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating
connector options.
All logic levels on J5 are 3.3V CMOS, except for the I
2
C ™ pins. These pins conform to 3.3V I
2
C rules.
Table 2 describes the J5 serial interface pins.
Table 2. J5: Serial Interface Pins
Pin No. Pin Name Signal Name I/O Type Pullup Function
J5.1 CNTL Unused
J5.2 GPIO0 M0 In/Out Low Data rate select input /
Modulator data output
J5.3 CLKX SCLK In None ADS1282 SPI ™ clock
J5.4 DGND DGND In/Out None Digital ground
J5.5 CLKR Unused
J5.6 GPIO1 M1 In/Out High Data rate select input /
Modulator data output
J5.7 FSX Unused
J5.8 GPIO2 MCLK Out Low Modulator clock output
J5.9 FSR DRDY Out None Data ready signal
J5.10 DGND DGND In/Out None Digital ground
J5.11 DX MOD/DIN In None ADS1282 SPI data in
J5.12 GPIO3 SUPSOR In High Power-supply regulator
Hi =
± 2.5V Lo = +5V
J5.13 DR DOUT Out None ADS1282 data out
J5.14 GPIO4 PDWN In High Power-down input
J5.15 INT DRDY Out None Data ready signal
J5.16 SCL SCL I
2
C n/a I
2
C clock
4 ADS1282EVM and ADS1282EVM-PDK User ' s Guide SBAU144C – March 2009 – Revised May 2011
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