Sinc Filter
(Decimate by
8 to 128)
Coefficient Filter
(FIR)
(Decimate by 32)
High-Pass Filter
(IIR)
Filter
MUX
To Output Register
From Modulator
Direct Modulator
Bit Stream
30
3
CAL
Block
Code
Clip
31
Filter Mode
(Register Select)
H(Z) =
1
Z
-
-
N
N(1
Z
-
)
-
1
5
AVSS
300mV < (VREFP or VREFN) < AVDD + 300mV
-
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
The ADS1282 reference inputs are protected by ESD
Digital Filter (continued)
diodes. In order to prevent these diodes from turning
Table 5. Digital Filter Selection
on, the voltage on either input must stay within the
range shown in
FILTR[1:0] BITS
DIGITAL FILTERS SELECTED
00
Bypass; modulator output mode
01
Sinc
10
Sinc + FIR
(6)
Sinc + FIR + HPF
11
Note that the minimum valid input for VREFN is
(low-pass and high-pass)
AVSS – 0.1V and maximum valid input for VREFP is
AVDD + 0.1V.
9.14.1 Sinc Filter Stage (Sinx/X)
A high-q5V reference voltage is necessary for
The sinc filter is a variable decimation rate, fifth-order,
achieving the best performance from the ADS1282.
low-pass filter. Data are supplied to this section of the
Noise and drift on the reference degrade overall
filter from the modulator at the rate of f
MOD
(f
CLK
/4).
system performance, and it is critical that special care
The sinc filter attenuates the high-frequency noise of
be given to the circuitry generating the reference
the modulator, then decimates the data stream into
voltages in order to achieve full performance. See the
parallel data. The decimation rate affects the overall
section
for
reference
data rate of the converter; it is set by the DR[2:0]
recommendations.
register bits, as shown in
.
9.14
Digital Filter
shows the scaled Z-domain transfer
function of the sinc filter.
The digital filter receives the modulator output and
decimates the data stream. By adjusting the amount
of filtering, tradeoffs can be made between resolution
and data rate: filter more for higher resolution, filter
less for higher data rate.
The digital filter is comprised of three cascaded filter
Where:
stages: a variable-decimation, fifth-order sinc filter; a
N = decimation ratio
(7)
fixed-decimation
FIR,
low-pass
filter
(LPF)
with
selectable phase; and a programmable, first-order,
Table 6. Sinc Filter Data Rates (CLK = 4.096MHz)
high-pass filter (HPF), as shown in
DECIMATION
SINC DATA RATE
The output can be taken from one of the three filter
DR[2:0] REGISTER
RATIO (N)
(SPS)
blocks, as
shows. To implement the digital
000
128
8,000
filter completely off-chip, select the filter bypass
setting (modulator output). For partial filtering by the
001
64
16,000
ADS1282, select the sinc filter output. For complete
010
32
32,000
on-chip filtering, activate both the sinc and FIR
011
16
64,000
stages. The HPF can then be included to remove dc
100
8
128,000
and low frequencies from the data.
shows the
filter options.
Figure 37. Digital Filter and Output Code Processing
18
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