Texas Instruments ADS127L11EVM, Руководство пользователя, Страница: 9 / 35

2.7 Clock Tree
Figure 2-6 shows the different clock options for the ADS127L11EVM. The default position for jumper (JP7) 1-2
routes the PHI digital controller board clock to the CLK pin on the ADS127L11 (U3). If the ADS127L11EVM is
used without the PHI board, then change the shunt on jumper (JP7) to position 2-3 to directly route the local
clock to ADS127L11 (U3).
Jumper (JP6) selects either the local 25-MHz oscillator (Y1) on the ADS127L11EVM board, or an external
clock supplied on the SMA connector (J14). The default position for jumper (JP6) 1-2 selects the local 25-MHz
oscillator (Y1). The ADS127L11EVM-PDK-GUI software by default uses the 24-MHz PHI clock source, but can
select the board clock source, 25-MHz (Y1) oscillator, or SMA connector (J14).
If the local 25-MHz oscillator (Y1) is used, then remove the shunt on jumper (JP3) to enable the oscillator. If an
external clock source is used, use a CMOS square-wave signal with an amplitude equal to IOVDD (1.8 V with
the PHI board) and a frequency within the specified range of the ADS127L11.
GND
1
2 3 4 5
J14
901-144-8RFX
GND
GND
100k
R91
IOVDD
Clock Tree
EXT Clock
GND
1
2
JP3
/OSC_EN
100nF
C55
1
2
3
JP6
TSW-103-07-G-S
1
2
3
JP7
TSW-103-07-G-S
EVM CLK
EXT CLK
EVM/EXT CLK
PHI CLK
100
R87
10pF
C58
DNP
GND
ADC.MCLK_IN
ADC.MCLK_OUT
EVM Clock
PHI Clock
100
R88
10pF
C59 DNP
GND
CLK
VCC
4
ST
1
GND 2
OUT 3
Y1
SG-210STF 25.0000ML3
0
R96
Vcc=3.63V MAX
Figure 2-6. Clock Tree
www.ti.com EVM Analog Interface
SBAU351 – APRIL 2021
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ADS127L11EVM-PDK Evaluation Module 9
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