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Texas Instruments ADS1271EVM Скачать руководство пользователя страница 13

ADS1271EVM Hardware Details

Table 14. CLKX Routing

CLKXMODE

CLKX Direction

CLX Connected to:

0 (Low)

Input

not connected

1 (High)

Output

CLK

5.6.1.3

OBCLKSEL Routing

OBCLKSEL selects between one of two master clock sources. When OBCLKSEL is high, the onboard
clock is active and used for the master clock. When OBCLKSEL is low, the master clock is taken from
EXTCLK on J2, and the onboard oscillator is disabled.

A pull-down resistor is installed on OBCLKSEL, making connection to an external clock the default setting.

Table 15. OBCLKSEL

OBCLKSEL

Master Clock is connected to:

0 (Low)

EXTCLK (J2.17)

1 (High)

On-board clock (U13)

5.6.2

ADS1271 Communication Modes

The ADS1271EVM supports both interface modes for the ADS1271. The interface mode is chosen using
switch S7, located near the top-right corner of the EVM.

Depending of the communication mode, J2 pin 9 (FSR on the bottom connector and FSOUT on the top
connector) connect to different signals (see

In SPI mode, FSR is connected to DRDY output signal from the first ADC (U8), while the second ADC
(U7) DRDY line is not connected. FSOUT is not connected.

In FSYNC mode, the FSYNC pins of both ADCs are tied together, and the signal on FSR is copied to the
top connector on pin FSOUT.

Table 16. J2 Pin 9 Routing

J2 Pin 9

Communications Mode

ADC1 (U8)

ADC2 (U7)

SPI Mode

Not connected

Not connected

FSOUT (Top side)

FSYNC Mode

FSYNC

FSYNC

SPI Mode

DRDY

Not connected

FSR (Bottom side)

FSYNC Mode

FSYNC

FSYNC

These configurations provide th capability of stacking ADS1271EVMs in either mode. To stack EVMs,
each EVM is required to operating in the same mode.

The MMB0 has the ability to determine the configuration of S7 by monitoring the FSDIR pin on J2. This
pin is high when FSOUT is active and FSR is an input, and low when FSOUT is disconnected and FSR is
an output.

5.7

Clock Source

The ADS1271 requires a clock signal for proper operation. Several options are available to source this
clock signal to the ADC.

5.7.1

Onboard Oscillator

A 27MHz clock oscillator is included on the EVM and is selected as the clock source for the device when
OBCLKSEL (J2.19) is high.

13

SBAU107C – November 2004 – Revised November 2014

ADS1271EVM and ADS1271EVM-PDK User's Guide

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Copyright © 2004–2014, Texas Instruments Incorporated

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Содержание ADS1271EVM

Страница 1: ...etails bill of materials and schematic The following related documents are available through the Texas Instruments web site at www ti com Table 1 EVM Compatible Device Data Sheets Literature Device Nu...

Страница 2: ...d that can be used with provided software to quickly evaluate the device This manual covers the operation of the ADS1271EVM PDK Throughout this document the abbreviation EVM and the term evaluation mo...

Страница 3: ...rence S4 Left Buffer connected to CH2 input S5 Left 2 5V reference connection to CH1 reference S6 Left Buffer connected to CH1 input S7 Left Hardware control of Format is floating J6 AV1 Installed AVD...

Страница 4: ...b After the main program is installed a dialog box appears with instructions for installing NI VISA 3 1 Runtime i Click OK to proceed ii Click Unzip and the archive extracts itself and automatically...

Страница 5: ...3 7 1 8VD 1 8V supply for ADC DVDD option 3 3V J3 9 3 3VD 3 3V supply for ADC DVDD option 5 0V J3 3 5VA 5 0V supply for ADC AVDD Positive supply for buffers 15V AVDD EVM supply J3 1 VA Power only requ...

Страница 6: ...click the Acquire button In Acquire mode you can only view the data from one channel at a time To choose channels use the Channel box 4 1 1 1 AC Analysis The basic AC analysis consists of the FFT grap...

Страница 7: ...SV file containing comma delimited decimal ADC values The first data column is Channel 1 followed by Channel 2 The data file can be imported into a spreadsheet for future inspection and analysis 4 2 C...

Страница 8: ...ector Select source of reference for U8 S6 U8 Analog Input selector Select source of analog input for U8 S7 Interface selector Select interface type FORMAT 5 2 Analog Connections 5 2 1 Analog Interfac...

Страница 9: ...Auxiliary Reference Input 2 Positive terminal J5 4 AUXREF2N Auxiliary Reference Input 2 Negative terminal J5 5 GND Ground 5 2 2 Analog Input Selection The analog input signals can be routed directly...

Страница 10: ...our EVMs can be stacked allowing for eight devices to be placed in a signal chain To accommodate stacking of EVMs J2 has some different connections on the top and the bottom side of the board Differen...

Страница 11: ...e U7 ADS1271 device while the shunt from J6 pins 5 to 6 applies this supply to the U8 ADS1271 The ADS1271 digital supply voltage DVDD is selected using J6 When a shunt is applied from J6 pins 9 to 10...

Страница 12: ...gardless of the logic level used on J2 Note that you are not required to include this circuitry in your own designs typically no glue logic is required to connect one or more ADS1271s to a processor 5...

Страница 13: ...he second ADC U7 DRDY line is not connected FSOUT is not connected In FSYNC mode the FSYNC pins of both ADCs are tied together and the signal on FSR is copied to the top connector on pin FSOUT Table 1...

Страница 14: ...low an external clock source should be connected to J2 17 In this setting the onboard clock oscillator is shut down 14 ADS1271EVM and ADS1271EVM PDK User s Guide SBAU107C November 2004 Revised Novembe...

Страница 15: ...RES 100K OHM 1 10W 5 0603 SMD Panasonic ERJ 3GEYJ104V 21 8 1K R7 R14 RES 1K OHM 1 10W 1 0603 SMD Panasonic ERJ 3EKF1001V 22 8 47 R15 R18 R23 R26 RES 47 OHM 1 10W 5 0603 SMD Panasonic ERJ 3GEYJ470V 23...

Страница 16: ...6 1 ADS1271EVM Schematic The schematic diagram is provided as a reference 16 ADS1271EVM and ADS1271EVM PDK User s Guide SBAU107C November 2004 Revised November 2014 Submit Documentation Feedback Copy...

Страница 17: ...S3 SW DP3T S5 SW DP3T C25 1N C23 100P C22 100P REFP REFN AUXREF1P AUXREF1N REFP AUXREF2P REFN AUXREF2N AMPOUT2P AMPOUT2N AIN1P AIN1N AIN0P AIN0N AUX1P AUX1N AUX2P AUX2N C14 10U ADCAVDD2 C19 10U C16 1...

Страница 18: ...tions table to consolidate connection information 5 Changed Sections 4 and 5 organization for clarity 6 Changed text to indicated minimum and maximum number of points for collection 7 Changed BOM to r...

Страница 19: ...ing the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repa...

Страница 20: ...essful communication This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna imped...

Страница 21: ...ified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors current sens...

Страница 22: ...REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE L...

Страница 23: ...sponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related inf...

Страница 24: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments ADS1271EVM ADS1271EVM PDK...

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