Texas Instruments ADS1271EVM, Руководство пользователя, Страница: 12 / 24

ADS1271EVM Hardware Details
www.ti.com
5.5 Reference Voltage
The ADS1271 requires an external voltage reference. Two switches, S3 and S5, select the source of the
reference for the two ADS1271s on the EVM. An external reference may be supplied through J1 pin 20 on
the ADS1271EVM, or through J4 and J5, the auxiliary analog input connectors. A 2.5V reference is
provided on the EVM for convenience. These different reference sources can be selected using S3 and
S5, as shown in
Table 12 .
CAUTION
Verify that the external reference voltage is within the safe operating limits
shown on the
ADS1271 data sheet before applying power to the EVM.
Table 12. Reference Selection Options - S3 and S5
S3/S5 Position Reference Inputs
Left Onboard 2.5V reference
Middle External Reference from J1.20 (REFP) referenced to J1.18
(REFN)
Right S3: AUXREF1 from J4.3 referenced to J4.4
S5: AUXREF2 from J5.3 referenced to J5.4
5.6 Communication Modes
The ADS1271EVM has a digital routing network which can help simulate several possible system
connections. The routing network also provides level-shifting, which allows the ADS1271 to be operated at
any supported logic level regardless of the logic level used on J2. Note that you are not required to include
this circuitry in your own designs; typically no glue logic is required to connect one or more ADS1271s to a
processor.
5.6.1 Digital Signal Routing Control
Routing is controlled by pins CLKRMODE, CLKXMODE, and OBCLKSEL on J2.
5.6.1.1 CLKR Routing
CLKRMODE controls the direction and connection of CLKR. When CLKRMODE is low, CLKR is an input
connected only to SCLK. When CLKRMODE is high, CLKR becomes an output connected to SCLK, and
SCLK is tied to CLK. This connection can be useful in both FSYNC and SPI modes.
A pull-down resistor is installed on CLKRMODE, making FSYNC mode the default setting.
Table 13. CLKR Routing
CLKRMODE CLKR Direction CLKR Connection to:
0 (Low) Input SCLK
1 (High) Output SCLK (SCLK tied to CLK)
5.6.1.2 CLKX Routing
When CLKXMODE is high, CLKX is an output connected to CLK. This setting is primarily useful for certain
configurations using the McBSP interface of various processors, where CLKX can be used as a reference
clock input for the serial port. When CLKXMODE is low, CLKX on J2 is unconnected.
A pull-down resistor is installed on CLKXMODE, making low the default setting.
12 ADS1271EVM and ADS1271EVM-PDK User's Guide SBAU107C – November 2004 – Revised November 2014
Submit Documentation Feedback
Copyright © 2004–2014, Texas Instruments Incorporated