Texas Instruments ADS126 EVM-PDK Series, Руководство пользователя, Страница: 12 / 38

ADS126xEVM Hardware
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2.5 Digital Interface, J1
The J1 header (top) and socket (bottom) provide access to the digital controls and serial data pins of the
ADS126x. These signals can be connected to a development platform for software development. All logic
levels are referenced to the digital supply voltage (the MMB0 provides a 3.3-V digital supply to the
ADS126xEVM through pin J5.9).
Table 3 describes the J1 serial interface pins.
Table 3. J1, Serial Interface Header
Pin Number
Function Signal Name (J1) Signal Name Function
1 2 Start conversion control
Unused START
(100-k Ω pull-up)
SPI clock SCLK 3 4 GND Ground
Unused 5 6 Reset (active low) or hold
RESET/PWDN low to power-down the
ADC (100-k Ω pull-up)
Serial port active low chip CS 7 8
Unused
select (100-k Ω pull-up)
Unused 9 10 GND Ground
Serial port data input DIN 11 12 Unused
Serial port data output and DOUT/DRDY 13 14
data ready indicator (active Unused
low)
Data ready indicator (active DRDY 15 16
SCL I
2
C clock (for EEPROM)
low)
Unused 17 18 GND Ground
Unused 19 20 SDA I
2
C data (for EEPROM)
NOTE: Keep all connections to the ADS126xEVM as short as possible. If jumper wiring is used to
connect a software development board to the ADS126xEVM, keep a ground connection
(wire) between boards close to all of the digital signals (wires). A large loop area between
ground and digital signals creates inductive connections and poor signal integrity.
When probing SPI communications, check the signal integrity near the receiving end (that is,
probe DIN at the ADS126x input, not at the SPI controller output).
12 ADS126xEVM-PDK SBAU206 – April 2015
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