1 Introduction
The ADC366xEVM is an evaluation board used to evaluate the ADC366x analog-to-digital converters (ADC)
from Texas Instruments. The ADC366x uses a serial LVDS interface to output the digital data. The serialized
LVDS interface supports output rates to 1 Gbps. The ADC366x can be operated in 'oversa decimating'
mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing
filter.
The ADC366xEVM is equipped with the following features:
• Transformer and FDA coupled analog inputs
• CDCE6214 clocking solution for on-board clocking
• Transformer coupled or single-ended clock inputs
• INA226 current shunt monitors for evaluating power consumption
• Power over mini-USB
• FMC connector
By default, the EVM is configured to receive external inputs for the sampling clock and analog input via AC-
coupled, transformer (balun) inputs. These transformers perform single-ended to differential conversion, and
provide a low noise/distortion passive input.
To exercise the full performance capabilities of this high performance SAR ADC, it is recommended to evaluate
the ADC in the default configuration, and then evaluate in other configurations (like onboard clocking or FDA
input), as required.
2 Equipment
This hardware setup procedure is written with the intent to use external clocking (sample clock and DCLKIN) and
transformer coupled analog inputs. Using onboard clocking and FDA driven analog inputs is an option, and
instructions are provided toward the end of this document to make the required hardware/software modifications.
2.1 ADC366xEVM Functionality
The ADC366xEVM receives power from the USB 2.0, +5 V rail, and is then converted to +3.3 VDC and +1.8
VDC. The ADC re1.8 VDC from the TPS62231 DC-DC converter. The power consumption of the 1.8 V
rail can be monitored (using the INA226) in the ADC35xxEVM GUI. USB-to-SPI communication is established
using the FTDI (FT4234H). The ADC clocks can be supplied externally or from the onboard PLL/Distributor
CDCE6214 (high quality external clocks are used to acheive best AC performance). The analog input can be AC
coupled through the Balun (ADT1-6T+) input, or DC (or AC) coupled with the onboard FDA (THS4541). The
analog input is 3.2 Vpp, and is driven a -1 dBFS (~2.8 Vpp) in all examples in this user's guide.
The ADC366x family has a +1.6 V voltage reference (VREF), and can be supplied internally or externally. By
default, the EVM is configured to supply an external voltage reference using the REF3318 (divided down to +1.6
V) and the OPA837 high speed amplifier to drive the voltage reference. At any time, the VREF can be changed
to internal reference by SPI write.
The ADC366x family uses an unbuffered analog input, so a glitch filter is required to attenuate the ADC sampling
glitch from when the sampling capacitors switch (sample/hold). The glitch filter acts as a low pass filter with an
corner frequency (Fc) at 30 MHz (accepts DC to 30 MHz).
The ADC366xEVM LVDS output data is routed to an FMC connector, and then connected to the LVDS
Interposer card. This interposer card then maps to the TSW1400EVM HSMC connector in order to capture the
ADC366xEVM SLVDS clock and data signals.
Introduction
2
ADC366xEVM Evaluation Module
SBAU366 – JANUARY 2021
Copyright © 2021 Texas Instruments Incorporated
