5.2 Hardware Setup: Real Decimation 16x Mode
• Connect ADC sampling clock source (SMA100A used) to J8. Set signal power to +15 dBm. 65 MSPS used in
this example.
• Connect DCLKIN clock source (SMA100A used) to J10. Set signal power to +13 dBm. 14.21875 MHz used in
this example
ADC sampling clock source and DCLKIN source must be frequency locked. If this is not performed,
the captured data will appear scrambled.
• If not already done, complete the remaining steps outlined in the section Setup Procedure.
5.3 External Clock: ADC35XX GUI Real Decimation Mode
To program the ADC364xEVM follow the steps written in the previous section titled "ADC35xx GUI: Real
Decimation Configuration". The only difference that must be observed in the GUI is "CDC Clock Enable" button
must be disabled (red) before selecting "Configure" in the ADC35xx GUI.
Figure 5-3. ADC35XX GUI: Disable CDC Clock Enable
External Clocking Hardware Setup
24
ADC364xEVM Evaluation Module
SBAU232 – OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
