SNAU127
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Config:
This tab configures various features and modes of the ADC08D1520 and is shown below. It accesses or
changes the following functions, all of which are controlled through Configuration Register 1.
Figure 10: Config Panel
•
nSD
– Second DCLK output – When this bit is 1b, the device only has one DCLK output and one
OR output. When this output is 0b, the device has two identical DCLK outputs and no OR output.
•
DCS
– Duty Cycle Stabilizer – When this bit is set to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set to 0b the stabilization circuit is disabled.
•
DCP
– DDR Clock Phase – This bit only has an effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the data bus edges (“0 degree phase”). When this bit is
set to 1b, the DCLK edges are placed in the middle of the data bit-cells (“90 degree phase”).
•
nDE
– DDR Enable – When this bit is set to 0b, data bus clocking follows the DDR mode
whereby a data word is output with each rising and falling edge of DCLK. When this bit is to a 1b,
data bus clocking follows the SDR mode whereby each data word is output with either the rising
or falling edge of DCLK, as determined by the OutEdge bit.
•
OV
– Output Voltage – This bit determines the LVDS outputs’ voltage amplitude and has the
same function as the OutV pin that is used in the Non-extended Control Mode. When this bit is set
to 1b, the normal output amplitude is used. When this bit is set to 0b, the reduced output amplitude
is used.
•
OED
– Output edge and demux control – This bit has two functions. When the device is in SDR
mode, this bit selects the DCLK edge with which the data words transition and has the same effect
as the OutEdge pin in the Non-Extended Control Mode. When this bit is set to 1b, the data outputs
change with the rising edge of DCLK+. When this bit is set to 0b, the data output changes with the
falling edge of DCLK+. When the device is in DDR mode, this bit selects the Non-demultiplexed
Mode when set to 1b. When the bit set to 0b, the device is programmed into the Demultiplexed
Mode. If the device is in DDR and Non-Demultiplexed Mode, then the DCLK has a 0 degree
phase relationship with the data; it is not possible to select the 90 degree phase relationship.
