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2.5.3 Operational Highlights for the Dead-Band Submodule

0

1

S2

1

0 S1

RED

Out

In

Rising edge

delay

(10-bit

counter)

(10-bit

counter)

delay

Falling edge

In

Out

FED

1

0 S3

0

S0

1

EPWMxA

EPWMxB

DBCTL[POLSEL]

DBCTL[OUT_MODE]

S5

DBCTL[IN_MODE]

1

0

S4

0

1

EPWMxA in

EPWMxB in

Dead-Band Generator (DB) Submodule

The following sections provide the operational highlights.

The dead-band submodule has two groups of independent selection options as shown in

Figure 2-28

.

•

Input Source Selection:

The input signals to the dead-band module are the EPWMxA and EPWMxB output signals from the
action-qualifier. In this section they will be referred to as EPWMxA In and EPWMxB In. Using the
DBCTL[IN_MODE) control bits, the signal source for each delay, falling-edge or rising-edge, can be
selected:

–

EPWMxA In is the source for both falling-edge and rising-edge delay. This is the default mode.

–

EPWMxA In is the source for falling-edge delay, EPWMxB In is the source for rising-edge delay.

–

EPWMxA In is the source for rising edge delay, EPWMxB In is the source for falling-edge delay.

–

EPWMxB In is the source for both falling-edge and rising-edge delay.

•

Output Mode Control:

The output mode is configured by way of the DBCTL[OUT_MODE] bits. These bits determine if the
falling-edge delay, rising-edge delay, neither, or both are applied to the input signals.

•

Polarity Control:

The polarity control (DBCTL[POLSEL]) allows you to specify whether the rising-edge delayed signal
and/or the falling-edge delayed signal is to be inverted before being sent out of the dead-band
submodule.

Figure 2-28. Configuration Options for the Dead-Band Submodule

Although all combinations are supported, not all are typical usage modes.

Table 2-13

documents some

classical dead-band configurations. These modes assume that the DBCTL[IN_MODE] is configured such
that EPWMxA In is the source for both falling-edge and rising-edge delay. Enhanced, or non-traditional
modes can be achieved by changing the input signal source. The modes shown in

Table 2-13

fall into the

following categories:

•

Mode 1: Bypass both falling-edge delay (FED) and rising-edge delay (RED)

Allows you to fully disable the dead-band submodule from the PWM signal path.

•

Mode 2-5: Classical Dead-Band Polarity Settings:

These represent typical polarity configurations that should address all the active high/low modes
required by available industry power switch gate drivers. The waveforms for these typical cases are
shown in

Figure 2-29

. Note that to generate equivalent waveforms to

Figure 2-29

, configure the

SPRU791D – November 2004 – Revised October 2007

ePWM Submodules

51

Submit Documentation Feedback

Содержание 28xxx

Страница 1: ...TMS320x28xx 28xxx Enhanced Pulse Width Modulator ePWM Module Reference Guide Literature Number SPRU791D November 2004 Revised October 2007...

Страница 2: ...2 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback...

Страница 3: ...alifier Event Priority 40 2 4 4 Waveforms for Common Configurations 41 2 5 Dead Band Generator DB Submodule 50 2 5 1 Purpose of the Dead Band Submodule 50 2 5 2 Controlling and Monitoring the Dead Ban...

Страница 4: ...ero Voltage Switched Full Bridge ZVSFB Converter 89 4 Registers 93 4 1 Time Base Submodule Registers 94 4 2 Counter Compare Submodule Registers 97 4 3 Action Qualifier Submodule Registers 99 4 4 Dead...

Страница 5: ...endent Modulation on EPWMxA and EPWMxB Active High 43 2 22 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 44 2 23 Up Count Pulse Placement Asymmetric Wa...

Страница 6: ...BPHS 94 4 3 Time Base Counter Register TBCTR 94 4 4 Time Base Control Register TBCTL 95 4 5 Time Base Status Register TBSTS 97 4 6 Counter Compare A Register CMPA 97 4 7 Counter Compare B Register CMP...

Страница 7: ...ounter Compare B Register CMPB Field Descriptions 98 4 8 Counter Compare Control Register CMPCTL Field Descriptions 99 4 9 Action Qualifier Output A Control Register AQCTLA Field Descriptions 100 4 10...

Страница 8: ...List of Tables 8 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback...

Страница 9: ...ital signal processors DSPs It also describes emulation features available on these DSPs SPRU712 TMS320x280x 2801x 2804x System Control and Interrupts Reference Guide describes the various interrupts...

Страница 10: ...rmation is located within that memory Tools Guides SPRU513 TMS320C28x Assembly Language Tools User s Guide describes the assembly language tools assembler and other tools used to develop assembly lang...

Страница 11: ...0 5 This application report has an option to download an example program that executes from RAM on the F2808 EzDSP SPRAAI1 Using Enhanced Pulse Width Modulator ePWM Module for 0 100 Duty Cycle Control...

Страница 12: ...Read This First 12 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback...

Страница 13: ...and other forms of power conversion The ePWM peripheral performs a digital to analog DAC function where the duty cycle is equivalent to a DAC analog value it is sometimes referred to as a Power DAC T...

Страница 14: ...feature Each ePWM module is indicated by a numerical value starting with 1 For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx indicates any instance The ePW...

Страница 15: ...WMxSOC To eCAP1 Submodule Overview Figure 1 1 Multiple ePWM Modules The order in which the ePWM modules are connected may differ from what is shown in Figure 1 1 See Section 2 2 3 2 for the synchroniz...

Страница 16: ...trip zone signals The trip zone signals can be configured as asynchronous inputs through the GPIO peripheral Time base synchronization input EPWMxSYNCI and output EPWMxSYNCO signals The synchronizati...

Страница 17: ...R_Dir CTR ZERO CTR CMPA CTR CMPB 16 16 16 16 16 16 Phase control EPWMxTZINT CTR ZERO 1 3 Register Mapping Register Mapping Figure 1 3 ePWM Submodules and Critical Internal Signal Interconnects Figure...

Страница 18: ...Edge Delay Count Register Trip Zone Submodule Registers TZSEL 0x0012 1 No Trip Zone Select Register TZCTL 0x0014 1 No Trip Zone Control Register 3 TZEINT 0x0015 1 No Trip Zone Enable Interrupt Regist...

Страница 19: ...e configured by software Topic Page 2 1 Overview 20 2 2 Time Base TB Submodule 23 2 3 Counter Compare CC Submodule 32 2 4 Action Qualifier AQ Submodule 37 2 5 Dead Band Generator DB Submodule 50 2 6 P...

Страница 20: ...itching events occur on the EPWMxA or EPWMxB output Action qualifier AQ Specify the type of action taken when a time base or counter compare submodule event occurs No action taken Output EPWMxA and or...

Страница 21: ...define TB_FREEZE 0x3 PHSEN bit define TB_DISABLE 0x0 define TB_ENABLE 0x1 PRDLD bit define TB_SHADOW 0x0 define TB_IMMEDIATE 0x1 SYNCOSEL bits define TB_SYNC_IN 0x0 define TB_CTR_ZERO 0x1 define TB_C...

Страница 22: ...define CHP6_8TH 0x5 define CHP7_8TH 0x6 TZSEL Trip zone Select CBCn and OSHTn bits define TZ_ENABLE 0x0 define TZ_DISABLE 0x1 TZCTL Trip zone Control TZA and TZB bits define TZ_HIZ 0x0 define TZ_FORCE...

Страница 23: ...2 1 illustrates the time base module s place within the ePWM Figure 2 1 Time Base Submodule Block Diagram You can configure the time base submodule for the following Specify the ePWM time base counte...

Страница 24: ...Status Register TBPHSHR 0x0002 No HRPWM extension Phase Register 1 TBPHS 0x0003 No Time Base Phase Register TBCTR 0x0004 No Time Base Counter Register TBPRD 0x0005 Yes Time Base Period Register 1 Thi...

Страница 25: ...M s time base counter This signal is high when the counter is increasing and low when it is decreasing CTR_max Time base counter equal max value TBCTR 0xFFFF Generated event when the TBCTR value reach...

Страница 26: ...rol hardware At a strategic point in time the shadow register s content is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously mo...

Страница 27: ...tion output EPWMxSYNCO The input synchronization for the first instance ePWM1 comes from an external pin The possible synchronization connections for the remaining ePWM modules are shown in Figure 2 4...

Страница 28: ...5 EPWM15SYNCO EPWM8SYNCI ePWM8 EPWM8SYNCO EPWM12SYNCI ePWM12 EPWM12SYNCO EPWM16SYNCI ePWM16 EPWM16SYNCO SYNCI eCAP1 Time Base TB Submodule Scheme 2 shown in Figure 2 5 is used by the 2804x devices whe...

Страница 29: ...and therefore has the same effect as a pulse on EPWMxSYNCI This feature enables the ePWM module to be automatically synchronized to the time base of another ePWM module Lead or lag phase control can b...

Страница 30: ...of each ePWM module must be set identically The proper procedure for enabling the ePWM clocks is as follows 1 Enable the individual ePWM module clocks This is described in the specific device version...

Страница 31: ...WN UP DOWN UP TBPHS value TBPRD value EPWMxSYNCI CTR_dir CTR zero CNT_max CTR PRD Time Base TB Submodule Figure 2 8 Time Base Down Count Mode Waveforms Figure 2 9 Time Base Up Down Count Waveforms TBC...

Страница 32: ...Time Base TB CTR PRD CTR 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM chopper PC Event Trigger and Interrupt ET Trip Zone TZ GPIO MUX ADC PIE PIE Counter Compare CC Submodule Figure 2 10 Time Base...

Страница 33: ...er compare A register TBCTR CMPA CTR CMPB Time base counter equals counter compare B register TBCTR CMPB Controls the PWM duty cycle if the action qualifier submodule is configured appropriately Shado...

Страница 34: ...to the registers synchronized with the hardware When shadowing is used updates to the active registers only occurs at strategic points This prevents corruption or spurious operation due to the regist...

Страница 35: ...the timing diagrams in Figure 2 13 through Figure 2 16 show when events are generated and how the EPWMxSYNCI signal interacts Figure 2 13 Counter Compare Event Waveforms in Up Count Mode NOTE An EPWMx...

Страница 36: ...RD value CTR CMPA CTR CMPB EPWMxSYNCI Counter Compare CC Submodule Figure 2 15 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 0 Count Down On Synchronization Event Figure 2 16 Counter Compa...

Страница 37: ...qualifier submodule is responsible for the following Qualifying and generating actions set clear toggle based on the following events CTR PRD Time base counter equal to the period TBCTR TBPRD CTR Zero...

Страница 38: ...compare B TBCTR CMPB Software forced event Asynchronous event initiated by software The software forced action is a useful asynchronous event This control is handled by registers AQSFRC and AQCSFRC T...

Страница 39: ...ontrol registers found at the end of this section For clarity the drawings in this document use a set of symbolic actions These symbols are summarized in Figure 2 19 Each symbol represents an action a...

Страница 40: ...r equals CMPA on up count CBU 1 1 To maintain symmetry for up down count mode both up events CAU CBU and down events CAD CBD can be generated for TBPRD Otherwise up events can occur only when the coun...

Страница 41: ...ng Use up down count mode to generate a symmetric PWM If you load CMPA CMPB on zero then use CMPA CMPB values greater than or equal to 1 If you load CMPA CMPB on period then use CMPA CMPB values less...

Страница 42: ...M period which when very short tend to be ignored by the system Figure 2 20 Up Down Count Mode Symmetrical Waveform The PWM waveforms in Figure 2 21 through Figure 2 26 show some common action qualifi...

Страница 43: ...Initialization Time EPwm1Regs TBPRD 600 Period 601 TBCLK counts EPwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 200 Compare B 200 TBCLK counts EPwm1Regs TBPHS 0 Set Phase regis...

Страница 44: ...modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB D The Do Nothing actions X are shown for completeness here but will not be shown on subsequent...

Страница 45: ...TL bit LOADAMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs AQCTLA bit PRD AQ_CLEAR EPwm1Regs AQCTLA bit CAU AQ_SET EPwm1Regs AQCTLB bit PRD...

Страница 46: ...TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLKOUT EPwm1Regs TBCTL bit CLKDIV TB_DIV1 EPwm1Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm1Regs CMPC...

Страница 47: ...CMPA half CMPA 400 Compare A 400 TBCLK counts EPwm1Regs CMPB 500 Compare B 500 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to zero EPwm1Regs TBCNT 0 clear TB counter EPwm1Regs TBCTL bit CTRMODE...

Страница 48: ...itialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwm1Regs CMPB 400 Compare B 400 TBCLK counts EPwm1Regs TBPHS 0 Set Phase regist...

Страница 49: ...zation Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA half CMPA 250 Compare A 250 TBCLK counts EPwm1Regs CMPB 450 Compare B 450 TBCLK counts EPwm1Regs TBPHS 0 Set Phase register to...

Страница 50: ...if the more classical edge delay based dead band with polarity control is required then the dead band submodule described here should be used The key functions of the dead band module are Generating a...

Страница 51: ...MODE bits These bits determine if the falling edge delay rising edge delay neither or both are applied to the input signals Polarity Control The polarity control DBCTL POLSEL allows you to specify whe...

Страница 52: ...gh No Delay X X 0 0 2 Active High Complementary AHC 1 0 1 1 3 Active Low Complementary ALC 0 1 1 1 4 Active High AH 0 0 1 1 5 Active Low AL 1 1 1 1 EPWMxA Out EPWMxA In No Delay 6 0 or 1 0 or 1 0 1 EP...

Страница 53: ...w Complementary ALC Active High AH Active Low AL RED FED Period Dead Band Generator DB Submodule Figure 2 29 shows waveforms for typical cases where 0 duty 100 Figure 2 29 Dead Band Waveforms for Typi...

Страница 54: ...venience delay values for various TBCLK options are shown in Table 2 14 Table 2 14 Dead Band Delay Values in S as a Function of DBFED and DBRED Dead Band Value Dead Band Delay in S 1 DBFED DBRED TBCLK...

Страница 55: ...power switching elements The key functions of the PWM chopper submodule are Programmable chopping carrier frequency Programmable pulse width of first pulse Programmable duty cycle of second and subse...

Страница 56: ...EPWMxA EPWMxB EPWMxA EPWMxA PWM Chopper PC Submodule Figure 2 31 PWM Chopper Submodule Operational Details Figure 2 32 shows simplified waveforms of the chopping action only one shot and duty cycle c...

Страница 57: ...OUT and OSHTWTH is the four control bits value from 1 to 16 Figure 2 33 shows the first and subsequent sustaining pulses and Table 7 3 gives the possible pulse width values for a SYSCLKOUT 100 MHz Fig...

Страница 58: ...subsequent pulses have been made programmable These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period and hence a programmabl...

Страница 59: ...te external fault or trip conditions and the ePWM outputs can be programmed to respond accordingly when faults occur The key functions of the Trip Zone submodule are Trip inputs TZ1 to TZ6 can be flex...

Страница 60: ...figured For more information see the GPIO section of the specific device version of the System Control and Interrupts Reference Guide listed in Section 1 Each TZn input can be individually configured...

Страница 61: ...enables TZ1 as a one shot event source for ePWM2 TZCTL TZA 1 EPWM2A will be forced high on a trip event TZCTL TZB 1 EPWM2B will be forced high on a trip event Scenario B A cycle by cycle event on TZ5...

Страница 62: ...4 TZ3 TZ2 TZ1 Trip logic Trip Trip CBC trip event OSHT trip event EPWMxA EPWMxB EPWMxA EPWMxB TZCTL TZB TZCTL TZA Async Trip Set Clear TZFLG CBC TZCLR CBC Set Clear TZFLG OST Trip Zone TZ Submodule Fi...

Страница 63: ...submodule are Receives event inputs generated by the time base and counter compare submodules Uses the time base direction information for up down event qualification Uses prescaling logic to issue in...

Страница 64: ...together and hence multiple modules can initiate an ADC start of conversion If two requests occur on one start of conversion line then only one will be recognized by the ADC Figure 2 39 Event Trigger...

Страница 65: ...r via software ETFRC These bits allow software forcing of an event Useful for debugging or s w intervention A more detailed look at how the various register bits interact with the Interrupt and ADC st...

Страница 66: ...ared This allows for one interrupt to be pending while one is serviced Writing to the INTPRD bits will automatically clear the counter INTCNT 0 and the counter output will be reset so no interrupts ar...

Страница 67: ...BCNT ETPS SOCBPRD ETCLR SOCB SOCB ETFRC SOCB ETSEL SOCBEN ETFLG SOCB ETSEL SOCBSEL 000 001 010 011 100 101 111 101 0 0 CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB CTR Zero CTR PRD Event Trigger ET Submodu...

Страница 68: ...ePWM Submodules 68 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback...

Страница 69: ...Multiple Buck Converters With Independent Frequencies 71 3 4 Controlling Multiple Buck Converters With Same Frequencies 75 3 5 Controlling Multiple Half H Bridge HHB Converters 78 3 6 Controlling Dua...

Страница 70: ...be enable switch open Sync flow through SyncOut connected to SyncIn Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in...

Страница 71: ...e ePWM module configured as a master can control two buck stages with the same PWM frequency If independent frequency control is required for each buck converter then one ePWM module must be allocated...

Страница 72: ...X EPWM4B Phase reg Master4 En EPWM4A 3 X Buck 1 Vout1 Vin1 EPWM1A Buck 2 Vin2 EPWM2A Vout2 Buck 4 Buck 3 Vin3 EPWM4A Vin4 EPWM3A Vout3 Vout4 SyncIn SyncIn SyncIn Controlling Multiple Buck Converters...

Страница 73: ...event triggers an interrupt CB A I P I P I P I Indicates this event triggers an ADC start of conversion Controlling Multiple Buck Converters With Independent Frequencies Figure 3 4 Buck Waveforms for...

Страница 74: ...SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2R...

Страница 75: ...rolling Multiple Buck Converters With Same Frequencies If synchronization is a requirement ePWM module 2 can be configured as a slave and can operate at integer multiple N frequencies of module 1 The...

Страница 76: ...CA Z I Z I A P CA CA CB CB CB CB CA CA CA CA CB CB CB CB Controlling Multiple Buck Converters With Same Frequencies Figure 3 6 Buck Waveforms for Figure 3 5 Note FPWM2 FPWM1 76 Applications to Power...

Страница 77: ...e 2 config EPwm2Regs TBPRD 600 Period 1200 TBCLK counts EPwm2Regs TBPHS 0 Set Phase register to zero EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Sl...

Страница 78: ...e with a single ePWM module This control can be extended to multiple stages Figure 3 7 shows control of two synchronized Half H bridge stages where stage 2 can operate at integer multiple N frequencie...

Страница 79: ...A CB CA Z Z A CB CA Pulse Center Z A CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA Controlling Multiple Half H Bridge HHB Converters Figure 3 8 Half H Bridge Waveforms for Figure 3 7 Note Here FPWM2 F...

Страница 80: ...DOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit ZRO AQ_SET set actions for EPWM1A EPwm2Regs AQCTLA bit...

Страница 81: ...CMPB Phase reg 3 Slave SyncOut X En EPWM3B EPWM3A Phase reg CTR CMPB CTR zero 4 Slave SyncOut X EPWM4A EPWM4B En SyncOut CTR zero CTR CMPB Phase reg Phase reg CTR CMPB CTR zero Slave 6 5 Slave X En Sy...

Страница 82: ...00 700 700 Z I A P CA CA Z I A P CA CA CA CA CA CA CA CA CA CA Controlling Dual 3 Phase Inverters for Motors ACI and PMSM Figure 3 10 3 Phase Inverter Waveforms for Figure 3 9 Only One Inverter Shown...

Страница 83: ...CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCT...

Страница 84: ...orrect operation As described in the TB module section a PWM module can be configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCTR register To illustrate this concep...

Страница 85: ...slave TBPHS registers 2 and 3 with values of 1 3 and 2 3 of the period value respectively For example if the period register is loaded with a value of 600 counts then TBPHS slave 2 200 and TBPHS slav...

Страница 86: ...cIn SyncIn EPWM1B CTR zero CTR CMPB SyncOut X EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 VIN EPWM2B EPWM2A EPWM3A EPWM3B VOUT 0 120 120 240 Controlling a 3 Phase Interleaved DC DC Converter Figure...

Страница 87: ...M3A EPWM3B 2 120 2 120 Z I Z I Z I Z I Z I A P CA CA A P CA CA A P CA CA Controlling a 3 Phase Interleaved DC DC Converter Figure 3 14 3 Phase Interleaved DC DC Converter Waveforms for Figure 3 13 SPR...

Страница 88: ...ADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit...

Страница 89: ...ase shifted full bridge or zero voltage switched full bridge Here the controlled parameter is not duty cycle this is kept constant at approximately 50 percent instead it is the phase relationship betw...

Страница 90: ...0 1200 FED ZVS transition ZVS transition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Figure 3 16 ZVS Full H Bridge Waveforms 9...

Страница 91: ...A 600 Set 50 fixed duty EPWM2A EPwm2Regs TBPHS 0 Set Phase register to zero initially EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UP Asymmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Re...

Страница 92: ...Applications to Power Topologies 92 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback...

Страница 93: ...nter Compare Submodule Registers 97 4 3 Action Qualifier Submodule Registers 99 4 4 Dead Band Submodule Registers 103 4 5 PWM Chopper Submodule Control Register 105 4 6 Trip Zone Submodule Control and...

Страница 94: ...e Register TBPHS 15 0 TBPHS R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 2 Time Base Phase Register TBPHS Field Descriptions Bits Name Value Description 15 0 TBPHS 0000 These bi...

Страница 95: ...nly used when the time base counter is configured in the up down count mode The PHSDIR bit indicates the direction the time base counter TBCTR will count after a synchronization event occurs and a new...

Страница 96: ...l to zero A write or read to the TBPRD register accesses the shadow register 1 Load the TBPRD register immediately without using a shadow register A write or read to the TBPRD register directly access...

Страница 97: ...Input Synchronization Latched Status Bit 0 Writing a 0 will have no effect Reading a 0 indicates no external synchronization event has occurred 1 Reading a 1 on this bit indicates that an external syn...

Страница 98: ...e same memory map address Figure 4 7 Counter Compare B Register CMPB 15 0 CMPB R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 7 Counter Compare B Register CMPB Field Descriptions...

Страница 99: ...Operates as a double buffer All writes via the CPU access the shadow register 1 Immediate mode Only the active compare B register is used All writes and reads directly access the active register for i...

Страница 100: ...ng 00 Do nothing action disabled 01 Clear force EPWMxA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 5 4...

Страница 101: ...nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 5 4 CAU Act...

Страница 102: ...is initiated This is a one shot forced event It can be overridden by another subsequent event on output B 1 Initiates a single s w forced event 4 3 ACTSFB Action when One Time Software Force B Is invo...

Страница 103: ...orcing is disabled and has no effect 1 0 CSFA Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes eff...

Страница 104: ...DE 1 1 and DBCTL IN_MODE 0 0 Other enhanced modes are also possible but not regarded as typical usage modes 00 Active high AH mode Neither EPWMxA nor EPWMxB is inverted default 01 Active low complemen...

Страница 105: ...0 7 0 DEL R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 15 Dead Band Generator Falling Edge Delay Register DBFED Field Descriptions Bits Name Description 15 10 Reserved Reserved...

Страница 106: ...T 0001 2 x SYSCLKOUT 8 wide 160 nS at 100 MHz SYSCLKOUT 0010 3 x SYSCLKOUT 8 wide 240 nS at 100 MHz SYSCLKOUT 0011 4 x SYSCLKOUT 8 wide 320 nS at 100 MHz SYSCLKOUT 0100 5 x SYSCLKOUT 8 wide 400 nS at...

Страница 107: ...M module 10 OSHT3 Trip zone 3 TZ3 Select 0 Disable TZ3 as a one shot trip source for this ePWM module 1 Enable TZ3 as a one shot trip source for this ePWM module 9 OSHT2 Trip zone 2 TZ2 Select 0 Disab...

Страница 108: ...zone pins can cause an event is defined in the TZSEL register Table 4 17 00 High impedance EPWMxB High impedance state 01 Force EPWMxB to a high state 10 Force EPWMxB to a low state 11 Do nothing no...

Страница 109: ...egister Table 4 21 1 CBC Latched Status Flag for Cycle By Cycle Trip Event 0 No cycle by cycle trip event has occurred 1 Indicates a trip event has occurred on a pin selected as a cycle by cycle trip...

Страница 110: ...is cleared If the TZFLG INT bit is cleared and any of the other flag bits are set then another interrupt pulse will be generated Clearing all flag bits will prevent further interrupts Figure 4 22 Trip...

Страница 111: ...decrementing 110 Enable event time base counter equal to CMPB when the timer is incrementing 111 Enable event time base counter equal to CMPB when the timer is decrementing 11 SOCAEN Enable the ADC St...

Страница 112: ...Counter Register These bits indicate how many selected ETSEL SOCBSEL events have occurred 00 No events have occurred 01 1 event has occurred 10 2 events have occurred 11 3 events have occurred 13 12 S...

Страница 113: ...s occurred 10 2 events have occurred 11 3 events have occurred 1 0 INTPRD ePWM Interrupt EPWMx_INT Period Select These bits determine how many selected ETSEL INTSEL events need to occur before an inte...

Страница 114: ...her interrupts will be generated until the flag bit is cleared Up to one interrupt can be pending while the ETFLG INT bit is still set If an interrupt is pending it will not be generated until after t...

Страница 115: ...5 4 Reserved Reserved 3 SOCB SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register The ETFLG SOCB flag bit will be set regardless 0 Has no effect Always re...

Страница 116: ...Registers 116 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback...

Страница 117: ...ified figure Figure 2 25 Modified figure Figure 2 26 Modified figure Section 2 6 3 Corrected register name from CHPCTL to PCCTL in the first paragraph of the section on operational highlights for the...

Страница 118: ...r Rising Edge Delay Register Reserved field Table 4 15 Modified the bit numbers of the Dead Band Generator Falling Edge Delay Register Reserved field Section 2 8 1 Updated description of event counter...

Страница 119: ...ce and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support...

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